초록 ▼

A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer i

A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.

대표청구항 ▼

[ We claim:] [1.] A semiconductor device comprising:a semiconductor chip having an inner pattern region where functional elements and wiring layers are formed, a bonding pad region outside said inner pattern region where bonding pads are formed, and a reserved region extending from an outer peripher

[ We claim:] [1.] A semiconductor device comprising:a semiconductor chip having an inner pattern region where functional elements and wiring layers are formed, a bonding pad region outside said inner pattern region where bonding pads are formed, and a reserved region extending from an outer periphery of said bonding pad region to a chip periphery, respectively defined on a substrate;an interlayer insulating layer including a coated insulating film, formed on said reserved region and said bonding pad region; anddummy via holes formed in said interlayer insulating layer in said reserved region or in said reserved region and said bonding pad region.