초록 ▼

A intelligent power management apparatus for use with a matched-filter. A multiplexer multiplexes shifted-in-phase chips and shifted-quadrature-phase chips from an in-phase-shift register and a quadrature-phase-shift register, respectively, to generate multiplexed chips. The multiplexed chips includ

A intelligent power management apparatus for use with a matched-filter. A multiplexer multiplexes shifted-in-phase chips and shifted-quadrature-phase chips from an in-phase-shift register and a quadrature-phase-shift register, respectively, to generate multiplexed chips. The multiplexed chips include alternating sets of shifted-in-phase chips and shifted-quadrature-phase chips. A controller generates a POWERDOWN signal when the multiplexed chips from a received-spread-spectrum signal do not have a particular-chip sequence. The controller generates an ACTIVATION signal when the multiplexed chips have the particular-chip sequence present. An adder tree generates a CORRELATION signal when the multiplexed chips have the particular-chip sequence and match or correlate with the settings of the adder tree. A number of AND gates inhibit the multiplexed chips from passing to the adder tree when the POWERDOWN signal is present, and pass the multiplexed chips to the adder tree when the ACTIVATION signal is present.

대표청구항 ▼

[ We claim:] [1.] An intelligent power management system for a matched filter, comprising:shifting means for shifting in-phase chips and quadrature-phase chips as shifted-in-phase chips and shifted-quadrature-phase chips, respectively;multiplexing means for multiplexing the shifted-in-phase chips an

[ We claim:] [1.] An intelligent power management system for a matched filter, comprising:shifting means for shifting in-phase chips and quadrature-phase chips as shifted-in-phase chips and shifted-quadrature-phase chips, respectively;multiplexing means for multiplexing the shifted-in-phase chips and the shifted-quadrature-phase chips to generate multiplexed chips including alternating sets of shifted-in-phase chips and sets of shifted-quadrature-phase chips;correlating means, responsive to an ACTIVATION signal, for attempting to correlate the multiplexed chips with settings of said correlating means and, responsive to said multiplexed chips having a particular-chip sequence correlated with the settings, for generating a CORRELATION signal, said correlating means, responsive to a POWERDOWN signal, for ceasing to attempt to correlate the multiplexed chips with settings of said correlating means; andcontrolling means for generating the ACTIVATION signal at all times during an acquisition phase, said controlling means, responsive to acquiring and tracking a received-spread-spectrum signal, for generating the ACTIVATION signal only when the multiplexed chips are likely to correlate with settings in said correlating means, and for generating the POWERDOWN signal when the multiplexed chips are unlikely to correlate with settings in said correlating means.