초록 ▼

A method and apparatus for assisting in the design of integrated circuits, which includes simulating functions, to be executed by the integrated circuit, in a parallel architecture machine comprising "Transputers." An allocation of the resources of this parallel architecture machine is monitored in

A method and apparatus for assisting in the design of integrated circuits, which includes simulating functions, to be executed by the integrated circuit, in a parallel architecture machine comprising "Transputers." An allocation of the resources of this parallel architecture machine is monitored in order to assess performance characteristics of the ASIC circuit to be designed.

대표청구항 ▼

[ What is claimed is:] [1.] A method for determining elements of an ASIC type integrated circuit provided with at least an arithmetic and/or logic unit, a non-volatile program memory and one or more working registers, said method comprising the following steps of:storing in a memory of a parallel ar

[ What is claimed is:] [1.] A method for determining elements of an ASIC type integrated circuit provided with at least an arithmetic and/or logic unit, a non-volatile program memory and one or more working registers, said method comprising the following steps of:storing in a memory of a parallel architecture machine a list of tasks that the integrated circuit, to be designed, must be made to perform;simulating a performance of these tasks with the parallel architecture machine having a scheduler circuit connected to a plurality of microprocessor circuits to make them carry out the tasks, wherein the scheduler circuit receives, from upline circuits, requests for performance of the tasks to be performed, chooses, for the performance of each task, one of the microprocessor circuits which is most suited to carry out the task, and directs the microprocessor to perform the task and to transmit processed signals to downline circuits; andobserving with a dedicated microprocessor and recording in memory a chronology and duration of performance of the tasks distributed by the scheduler circuit so that the chronology and the duration, in this performance of the tasks, may be examined to determine whether there may be a conflict of processing resources and to determine the elements of the ASIC type integrated circuit to be made.