$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Suspend/resume capability for a protected mode microprocessor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-001/30
출원번호 US-0457931 (1995-06-01)
발명자 / 주소
  • Foster Mark J.
  • Fakhruddin Saifuddin T.
  • Walker James L.
  • Mendelow Matthew B.
  • Sun Jiming
  • Brahman Rodman S.
  • Krau Michael P.
  • Willoughby Brian D.
  • Maddix Michael D.
  • Belt Steven L.
  • Hovey
출원인 / 주소
  • Vantus Technologies, Inc.
대리인 / 주소
    Smith
인용정보 피인용 횟수 : 42  인용 특허 : 63

초록

A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of ope

대표청구항

[ The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:] [1.] An apparatus, comprising: a main processor having a normal operational mode, a first reduced power mode, and a second reduced power mode different from said first reduced power mod

이 특허에 인용된 특허 (63)

  1. Arroyo Ronald X. (Elgin TX) Day Michael N. (Austin TX) Edrington Jimmie D. (Georgetown TX) Hanna James T. (Austin TX) Hunt Gary T. (Austin TX) Pancoast Steven T. (Austin TX), Apparatus and method for suspending and resuming software applications on a computer.
  2. Hanaoka Masaaki (Suwa JPX), Apparatus for providing continuity of operation in a computer.
  3. Carter Robert R. (Cypress TX) Garner Paul M. (The Woodlands TX) Cepulis Darren J. (Houston TX) Boone Carrie (Houston TX), Apparatus for reducing computer system power consumption.
  4. Canova ; Jr. Francis J. (Boynton Beach FL) Katz Neil A. (Parkland FL) Pollitt Richard F. (Jensen Beach FL) Suarez Leopoldo L. (Boca Raton FL) Astarabadi Shaun (Irvine CA) Frank C. William (Irvine CA), Battery operated computer power management system.
  5. Pusic Vladi (San Jose CA) George Benjamin T. (Sunnyvale CA) Smith Monte E. (St. Paul MN) Johnson Craig B. (Shoreview MN), Cache/disk file status indicator with data protection feature.
  6. Tamaki Kazuyoshi (Nagoya JPX), Circuit arrangement for preventing a microcomputer from malfunctioning.
  7. Lies Kenneth A. (Lubbock TX), Clocked logic low power standby mode.
  8. Rose Frederick A. (Rte. 3 ; Box 529 Fort Atkinson WI 53538) DeWitt Christopher P. (Rte. 3 ; Koshkonong Lake Rd. Fort Atkinson WI 53538), Communications management system having multiple power control modes.
  9. Marrington S. Paul (Fyshwick CA AUX) Kiankhooy-Fard Paul (San Diego CA) Zecos P. (Del Mar CA) Rudaw Geoffrey (Nancet NY), Computer power system.
  10. Marrington S. Paul (P.O. Box 34 Fyshwick CA AUX 2609) Kiankhooy-Fard Paul (1165 Archer St. San Diego CA 92109) Zecos Paul (13367 Caminito Mar Villa Del Mar CA) Rudaw Geoffrey (43 Argow Pl. Nanuet NY , Computer power system.
  11. Kaneda Saburo (Yokohama JPX) Murakami Kazuaki (Kawasaki JPX), Computer system for controlling virtual machines.
  12. Nagasawa Kunihiko (Tokyo JPX), Computer system with a back-up power supply.
  13. Satoh Masaharu (Nara JPX) Hashimoto Sadakatsu (Nara JPX), Control system for multi-processor.
  14. Hillion Herv (Eindhoven NLX), Data processing apparatus with energy saving clocking device.
  15. McAnlis James C. (Bangor GB5) Kumar Kuldip (Gateshead PA GB2) Gould Robert T. M. (Downington PA), Data processor system including data-save controller for protection against loss of volatile memory information during p.
  16. Bush Kenneth L. (Cypress TX) Perry Ralph S. (Houston TX), Disk drive activity indicator.
  17. Morehouse James H. (Jamestown CO) Andrews ; Jr. Thomas L. (Boulder CO) Blagaila John H. (Boulder CO) Furay David M. (Boulder CO) Johnson Terry G. (Longmont CO), Disk drive apparatus using dynamic loading/unloading.
  18. Saitou Yosio (Oome JPX), Display panel open/closed detection mechanism, and portable electronic apparatus using the same.
  19. Swartz Jack S. (San Jose CA), Dual mode actuator for disk drive useful with a portable computer.
  20. Garner Paul M. (The Woodlands TX) Boone Carrie (Houston TX) Cepulis Darren J. (Houston TX), Dynamically configurable portable computer system.
  21. Kimura Toshiyuki (Kawagoe JPX) Yamazaki Youichi (Kawagoe JPX) Nonaka Yoshiya (Kawagoe JPX) Go Yasunao (Kawagoe JPX) Endo Fumio (Kawagoe JPX) Komata Hiroyuki (Kawagoe JPX) Syoji Mitsuo (Kawagoe JPX), Electronic unit operable in conjunction with body unit.
  22. Poret Mark (Mesa AZ) McKinley Jeanne (Chandler AZ), In-circuit emulator.
  23. Suzuki Naoshi (Kanagawa JPX) Uno Shunya (Machida JPX), Information processing system having power saving control of the processor clock.
  24. Little Wendell L. (Carrollton TX), Integrated circuit with watchdog timer and sleep control logic which places IC and watchdog timer into sleep mode.
  25. Yorimoto Yoshikazu (Tokyo JPX) Takahashi Masashi (Tokyo JPX) Hirano Seiji (Tokyo JPX), Integrated-circuit card with active mode and low power mode.
  26. Adams Matthew K. (Dallas TX) Little Wendell L. (Denton TX) Grider Stephen N. (Farmers Branch TX), Interface: interrupt masking with logical sum and product options.
  27. Raasch Charles F. (El Toro CA) Kim Jason S. M. (Los Angeles CA), Internal interrupt controller for a peripheral controller.
  28. James David V. (Palo Alto CA), Interrupt system using masking register in processor for selectively establishing device eligibility to interrupt a part.
  29. Takayama Shigeru (Tokyo JPX), Interruption control circuit.
  30. Bartling James E. (Dallas TX) Little Wendell L. (Denton TX) Deierling Kevin E. (Dallas TX), Isolation gates to permit selective power-downs within a closely-coupled multi-chip system.
  31. Jones Steven W. (Wood Dale IL) Alifen Chandra (Hoffman Estates IL), Line power failure scheme for a gaming device.
  32. Cole James F. (Palo Alto CA) McNamara James H. (Santa Cruz CA), Low-power, standby mode computer.
  33. Cole James F. (Palo Alto CA) McNamara James H. (Santa Cruz CA), Low-power, standby mode computer.
  34. Nishimura Kosuke (Yamatokoriyama JPX), Memory contents confirmation.
  35. Belt Steven L. (Stevensville MI) Ruthenbeck Mark A. (Lincoln Township ; Berrien County MI) Foster Mark J. (Lincoln Township ; Berrien County MI) Barnes Brian C. (Benton Township ; Berrien County MI) , Method and apparatus facilitating communication between two keyboards and a single processor.
  36. Fakhruddin Saifuddin T. (St. Joseph MI) Foster Mark J. (Lincoln Township ; Berrien County MI) Hovey Scott A. (St. Joseph MI) Walker James L. (Benton Harbor MI) Vanderheyden Randy J. (St. Joseph Towns, Method and apparatus facilitating use of a hard disk drive in a computer system having suspend/resume capability.
  37. Fakruddin Saifee (St. Joseph MI) Foster Mark J. (Stevensville MI), Method and apparatus for battery-power management using load-compensation monitoring of battery discharge.
  38. Letwin James (Kirkland WA), Method and operating system for executing programs in a multi-mode microprocessor.
  39. Watanabe Minoru (Tokyo JPX), Microcomputer which enters sleep mode for a predetermined period of time on response to an activity of an input/output d.
  40. Arroyo Ronald X. (Elgin TX) Hanna James T. (Austin TX), Multi-frequency clock generation with low state coincidence upon latching.
  41. Yurchenco James R. (Palo Alto CA), Multiple independent input peripherals.
  42. Hirano Takaaki (Nara JPX) Kamuro Setsufumi (Yamatokoriyama JPX) Yamaguchi Akira (Nara JPX) Tanimoto Junichi (Tenri JPX) Okada Mikiro (Nara JPX), Peripheral unit for a microprocessor system.
  43. Kobayashi Takaichi (Itsukaichi JPX), Personal computer having condition indicator.
  44. Murez James D. (Santa Monica CA), Portable computer enclosure.
  45. Fung Henry T. S. (San Jose CA), Power conservation apparatus having multiple power reduction levels dependent upon the activity of the computer system.
  46. Perry Richard A. (Charlotte NC) Stant Vernon L. (Richmond VA), Power conservation in microprocessor controlled devices.
  47. Zato Thomas J. (Palatine IL), Power loss compensation for programmable memory control system.
  48. Smith R. Steven (Saratoga CA) Hanlon Mike S. (San Jose CA) Bailey Robert L. (San Jose CA), Power management for a laptop computer with slow and sleep modes.
  49. Juzswik David L. (Dearborn Heights MI) Webb Nathaniel (Detroit MI) Floyd William M. (Livonia MI), Power-conserving control system for turning-off the power and the clocking for data transactions upon certain system ina.
  50. Culley Paul R. (Houston TX), Priority arbitration circuit for processor access.
  51. Mori Shosuke (Tokyo JPX), Processor having plural initial loading programs for loading different operating systems.
  52. Watts ; Jr. LaVaughn F. (Temple TX) Wallace Steven J. (Temple TX), Real-time power conservation for portable computers.
  53. Arai Makoto (Tokyo JPX), Resume control system and method for executing resume processing while checking operation mode of CPU.
  54. Niijima Shinji (Tokyo JPX), Single-chip mircocomputer with clock-signal switching function which can disable a high-speed oscillator to reduce power.
  55. Reddy Chandrashekar M. (Santa Clara CA) Hirose Scott D. (San Jose CA) Cho Sung-Soo (Sunnyvale CA) Kardach James P. (San Jose CA) Farrer Steven M. (Santa Clara CA) Roberts Meeling (Fremont CA), Slow memory refresh in a computer with a limited supply of power.
  56. Nocilini, John D.; Sharp, Ronald E.; Cuadra, Emilio J., Stanby mode controller utilizing microprocessor.
  57. Nguyen Au H. (Santa Clara CA) Gollabinnie Aurav R. (San Jose CA), Suspend/resume apparatus and method for reducing power consumption in battery powered computers.
  58. Lee Robert H. J. (Palo Alto CA) Kenny John D. (Sunnyvale CA), Switchable clock circuit for microprocessors to thereby save power.
  59. Chang Bo E. (22 Yearling Ct. Rockville MD 20850), Three layered laptop computer.
  60. Kardach James (San Jose CA) Mathews Gregory (Cupertino CA) Nguyen Cau (Milpitas CA) Cho Sung S. (Sunnyvale CA) Sivamani Kameswaran (Sunnyvale CA) Vannier David (Cupertino CA) Wong Shing (Cupertino CA, Transparent system interrupt.
  61. Byrd Kerry (Falls Church VA), Work-saving system for preventing loss in a computer due to power interruption.
  62. Alley Lynn D. (Riverton UT) Alley Stephen W. (Bountiful UT) Sadlier William K. (Salt Lake City UT) Burton Richard A. (Salt Lake City UT), Wrap-around auxiliary keyboard.
  63. Director Dennis (3116 Central St. Evanston IL 60201), Write protect control circuit for computer hard disc systems.

이 특허를 인용한 특허 (42)

  1. Bonola, Thomas J.; Faasse, Scott P.; Depew, Kevin G.; Harsany, John S., BIOS-based systems and methods of processor power management.
  2. Aguilar, Maximino; Gupta, Sanjay; Kim, Roy Moonseuk; Lo, Yuan-Chang; Stafford, James Michael, Compact diagnostic connector for a motherboard of data processing system.
  3. Timothy J. Torzewski ; William J. Armstrong, Jr., Computer system, program product and method for tracking asynchronous I/O with timeout support.
  4. Ghose, Kanad, Continuous run-time validation of program execution: a practical approach.
  5. Matsui, Hideki; Fujii, Kuniaki, Control device and control method.
  6. Gil,Myeong Ho, Device for detection of power-off.
  7. Muir, Robert Lindley; Boesen, John; Jones, Mike, Gaming machine power fail enhancement.
  8. Muir, Robert Lindley; Boesen, John; Jones, Mike, Gaming machine power fail enhancement.
  9. Muir, Robert Lindley; Boesen, John; Jones, Mike, Gaming machine power fail enhancement.
  10. Taniguchi,Hisashi; Esaki,Tetsuya; Aoki,Tomoyuki, Information processing apparatus with a function for low-power operation by controlling a power supply to a recording section of a recording medium and a computer individually.
  11. Fuisz, Richard C., Method and apparatus for bouncing electronic messages.
  12. Fuisz, Richard C., Method and apparatus for bouncing electronic messages.
  13. Fuisz,Richard C., Method and apparatus for bouncing electronic messages.
  14. Fuisz,Richard C., Method and apparatus for bouncing electronic messages.
  15. Richard C. Fuisz, Method and apparatus for bouncing electronic messages.
  16. Wu, Chia-Chuan, Method and apparatus for integrating personal computer and electronic device functions.
  17. Wu, Chia-Chuan, Method and apparatus for integrating personal computer and electronic device functions.
  18. Christensen Alan ; Kocher Fritz, Method and apparatus for preventing inadvertent power management time-outs.
  19. Jackson David R. ; Cross Leonard W. ; Jacobs Robert A. ; Oztaskin Ali S., Method and apparatus for supporting power conservation operation modes.
  20. Beelitz Alan E., Method and system for preventing unauthorized access to a computer program.
  21. Baber Stephen B. ; Britton Kathryn H. ; Hind John R. ; Housel ; III Barron C. ; Wesley Ajamu Akinwunmi, Methods, systems and computer program products for differencing data communications using a message queue.
  22. Baber,Stephen C.; Britton,Kathryn Heninger; Hind,John R.; Housel,Barron C.; Venkatapathy,Chandrasekaran; Wanderski,Michael C.; Wesley,Ajamu, Methods, systems and computer program products for restartable multiplexed file transfers.
  23. Kathryn H. Britton ; Andrew P. Citron ; Barron C. Housel, III ; Ajamu Akinwunmi Wesley, Methods, systems and computer program products for synchronization of queue-to-queue communications.
  24. Baber, Stephen B.; Britton, Kathryn H.; Hind, John R.; Housel, III, Barron C.; Wesley, Ajamu Akinwunmi, Methods, systems and computer program products for transferring a file using a message queue.
  25. Long, Thomas C., Non-volatile memory drive partitions within microcontrollers.
  26. Housel ; III Barron Cornelius ; Shields Ian Beaumont ; Meriwether Teresa Anne, Persistent cache synchronization and start up system.
  27. Yang, Robert K.; Fuiz, Richard C.; Myers, Garry L.; Fuiz, Joseph M., Process for making a film having a substantially uniform distribution of components.
  28. Yang, Robert K.; Fuisz, Richard C.; Myers, Garry L.; Fuisz, Joseph M., Process for manufacturing a resulting multi-layer pharmaceutical film.
  29. Yang, Robert K.; Fuisz, Richard C.; Myers, Garry L.; Fuisz, Joseph M., Process for manufacturing a resulting multi-layer pharmaceutical film.
  30. Yang, Robert K.; Fuisz, Richard C.; Myers, Garry L.; Fuisz, Joseph M., Process for manufacturing a resulting pharmaceutical film.
  31. De Groote, Stephen P., Reserve release proxy.
  32. Fleischmann, Marc; Anvin, H. Peter, Restoring processor context in response to processor power-up.
  33. Fleischmann, Marc; Anvin, H. Peter, System and method for saving and restoring a processor state without executing any instructions from a first instruction set.
  34. Yang, Ping; Gopalan, Kartik, System and method for security and privacy aware virtual machine checkpointing.
  35. Yang, Ping; Gopalan, Kartik, System and method for security and privacy aware virtual machine checkpointing.
  36. Ghose, Kanad, System and method for validating program execution at run-time.
  37. Yang, Robert K.; Fuisz, Richard C.; Myers, Garry L.; Fuisz, Joseph M., Thin film with non-self-aggregating uniform heterogeneity and drug delivery systems made therefrom.
  38. Yang, Robert K.; Fuisz, Richard C.; Myers, Garry L.; Fuisz, Joseph M., Uniform films for rapid dissolve dosage form incorporating taste-masking compositions.
  39. Yang, Robert K.; Fuisz, Richard C.; Myers, Garry L.; Fuisz, Joseph M., Uniform films for rapid dissolve dosage form incorporating taste-masking compositions.
  40. Myers, Garry L.; Sanghvi, Pradeep; Verrall, Andrew Philip; Francis, Vimala; Brooks, Laura, Uniform films for rapid-dissolve dosage form incorporating anti-tacking compositions.
  41. Myers, Garry L.; Sanghvi, Pradeep; Verrall, Andrew Philip; Francis, Vimala; Moss, Laura, Uniform films for rapid-dissolve dosage form incorporating anti-tacking compositions.
  42. Marc D. Alexander ; Peter A. Woytovech, Using RTC wake-up to enable recovery from power failures.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로