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Pulse signal transfer unit employing post charge logic 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/0185
  • H03K-019/017
출원번호 US-0673210 (1996-06-27)
우선권정보 KR-0018875 (1995-06-30)
발명자 / 주소
  • Lee Jae Jin,KRX
출원인 / 주소
  • Hyundai Electronics Industries Co., Ltd., KRX
대리인 / 주소
    Nath
인용정보 피인용 횟수 : 43  인용 특허 : 0

초록

A pulse signal transfer unit employing post charge logic, comprising a buffering circuit for transferring data with a specified logic value through a data transfer line, a PMOS transistor for supplying a voltage from a voltage source to the data transfer line to initialize a signal on the data trans

대표청구항

[ What is claimed is:] [1.] A pulse signal transfer unit employing post charge logic, comprising:buffering means for transferring data with a specified logic value through a data transfer line;initialization means for supplying a voltage from a voltage source to said data transfer line to initialize

이 특허를 인용한 특허 (43)

  1. Pitkethly, Scott; Masleid, Robert Paul, Advanced repeater utilizing signal distribution delay.
  2. Pitkethly,Scott; Masleid,Robert Paul, Advanced repeater utilizing signal distribution delay.
  3. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  4. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  5. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  6. Pitkethly,Scott, Advanced repeater with duty cycle adjustment.
  7. Masleid, Robert Paul; Dholabhai, Vatsal, Circuit with enhanced mode and normal mode.
  8. Masleid, Robert Paul; Kowalczyk, Andre, Circuits and methods for detecting and assisting wire transitions.
  9. Masleid,Robert Paul; Kowalczyk,Andre, Circuits and methods for detecting and assisting wire transitions.
  10. Masleid,Robert Paul; Kowalczyk,Andre, Circuits and methods for detecting and assisting wire transitions.
  11. Masleid, Robert, Circuits, systems and methods relating to a dynamic dual domino ring oscillator.
  12. Masleid,Robert P., Circuits, systems and methods relating to dynamic ring oscillators.
  13. Masleid, Robert Paul, Column select multiplexer circuit for a domino random access memory array.
  14. Masleid, Robert Paul, Configurable delay chain with stacked inverter delay elements.
  15. Masleid,Robert Paul, Configurable delay chain with stacked inverter delay elements.
  16. Masleid, Robert Paul, Configurable delay chain with switching control for tail delay elements.
  17. Masleid, Robert Paul, Configurable tapered delay chain with multiple sizes of delay elements.
  18. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  19. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  20. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  21. Lee Jae Jin,KRX, Data transfer device with a post charge logic.
  22. Masleid, Robert P, Dynamic ring oscillators.
  23. Masleid, Robert P, Inverting zipper repeater circuit.
  24. Masleid, Robert P., Inverting zipper repeater circuit.
  25. Masleid, Robert Paul, Inverting zipper repeater circuit.
  26. Masleid, Robert, Leakage efficient anti-glitch filter.
  27. Masleid,Robert Paul, Leakage efficient anti-glitch filter with variable delay stages.
  28. Masleid, Robert Paul, Power efficient multiplexer.
  29. Masleid, Robert Paul, Power efficient multiplexer.
  30. Masleid, Robert Paul, Power efficient multiplexer.
  31. Masleid, Robert Paul, Power efficient multiplexer.
  32. Masleid,Robert Paul, Power efficient multiplexer.
  33. Masleid, Robert Paul; Dholabhai, Vatsal; Klingner, Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  34. Masleid,Robert Paul; Dholabhai,Vatsal; Klingner,Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  35. Masleid,Robert Paul; Dholabhai,Vatsal; Stoiber,Steven Thomas; Singh,Gurmeet, Repeater circuit with high performance repeater mode and normal repeater mode.
  36. Masleid, Robert Paul; Dholabhai, Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  37. Masleid,Robert Paul; Dholabhai,Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  38. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  39. Stoiber, Steven T.; Siu, Stuart, Ring based impedance control of an output driver.
  40. Nakamura Hiroya, Signal line driver having reduced transmission delay time and reduced power consumption.
  41. Masleid, Robert P.; Burr, James B., Stacked inverter delay chain.
  42. Masleid,Robert P.; Burr,James B., Stacked inverter delay chain.
  43. Bobba, Sudhakar; Trivedi, Pradeep, Transmission gate based signal transition accelerator.
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