[특허]Microprocessor using an instruction field to expand the condition flags and a computer system employing the microprocess

Microprocessor using an instruction field to expand the condition flags and a computer system employing the microprocess 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-009/32
출원번호	US-0914698 (1997-08-19)
발명자 / 주소	Dutton Drew J. Christie David S.
출원인 / 주소	Advanced Micro Devices, Inc.
대리인 / 주소	Conley, Rose & TayonKivlin
인용정보	피인용 횟수 : 36 인용 특허 : 0

초록 ▼

A microprocessor is provided which is configured to detect the presence of segment override prefixes in instruction code sequences being executed in flat memory mode, and to use the prefix value or the value stored in the associated segment register to selectively enable condition flag modification for instructions. An instruction which modifies the condition flags and a branch instruction intended to branch based on the condition flags set by the instruction may be separated by numerous instructions which do not modify the condition flags. When the branch instruction is decoded, the condition flags it depends on may already be available. In another embodiment of the present microprocessor, the segment register override bytes are used to select between multiple sets of condition flags. Multiple conditions may be retained by the microprocessor for later examination. Conditions which a program utilizes multiple times in a program may be maintained while other conditions may be generated and utilized.

대표청구항 ▼

[ What is claimed is:] [1.] A microprocessor comprising:an address translation unit configured to generate a physical address from a logical address and a segment value;a plurality of segment registers coupled to said address translation unit wherein the plurality of segment registers store different segment values when a flat memory address translation mode is not in use, and wherein each of said plurality of segment registers stores a same segment value when the flat memory address translation mode is in use;a first control unit coupled to said address translation unit wherein said first control unit is configured to detect an instruction field indicative of one of said plurality of segment registers and to convey a signal to said address translation unit indicative of said one of said plurality of segment registers;a configuration register for storing a first value when the flat memory address translation mode is in use, and a second value when the flat memory address translation mode is not in use; andan execution unit for executing instructions wherein said execution unit is configured to modify the execution of said instructions in response to said signal and said first value.

이 특허를 인용한 특허 (36)

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Henry, G. Glenn; Hooker, Rodney E.; Parks, Terry, Apparatus and method for instruction-level specification of floating point format.
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Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Apparatus and method for providing extended address modes in an existing instruction set for a microprocessor.
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Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Apparatus and method for selective control of condition code write back.
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Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Apparatus and method for selective control of results write back.
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Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Apparatus and method for selective memory attribute control.
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Christie, David S., Central processing unit (CPU) accessing an extended register set in an extended register mode.
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Ando Hideki,JPX, Compiler for converting source program into object program having instruction with commit condition.
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Combs, Jonathan D.; Brandt, Jason W.; Valentine, Robert; Smith, Kevin B.; Ansari, Zia; Loktyukhin, Maxim, Conditional execution support for ISA instructions using prefixes.
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Arakawa, Fumio, Data processor including prefix instruction selecting a flag out of a plurality of flags generated by a subsequent instruction operating on multiple operand sizes in parallel.
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Arakawa, Fumio, Flag generation and use in processor with same processing for operation on small size operand as low order bits portion of operation on large size operand.
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Gschwind, Michael Karl; Montoye, Robert Kevin; Olsson, Brett; Wellman, John-David, Implementing instruction set architectures with non-contiguous register file specifiers.
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Gschwind, Michael Karl; Montoye, Robert Kevin; Olsson, Brett; Wellman, John-David, Implementing instruction set architectures with non-contiguous register file specifiers.
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Gschwind,Michael Karl; Montoye,Robert Kevin; Olsson,Brett; Wellman,John David, Implementing instruction set architectures with non-contiguous register file specifiers.
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Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Mechanism for extending the number of registers in a microprocessor.
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O'Connor Dennis M., Method and apparatus for speeding sequential access of a set-associative cache.
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Thomas L. Drabenstott ; Gerald G. Pechanek ; Edwin F. Barry ; Charles W. Kurak, Jr., Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution.
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Gschwind, Michael Karl; Montoye, Robert Kevin; Olsson, Brett; Wellman, John-David, Methods for generating code for an architecture encoding an extended register specification.
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Gschwind, Michael Karl; Montoye, Robert Kevin; Olsson, Brett; Wellman, John-David, Methods for generating code for an architecture encoding an extended register specification.
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Gschwind, Michael Karl; Montoye, Robert Kevin; Olsson, Brett; Wellman, John-David, Methods for generating code for an architecture encoding an extended register specification.
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McGrath, Kevin J., Mode dependent segment use with mode independent segment update.
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Henry, G. Glenn; Hooker, Rodney E.; Parks, Terry, Non-temporal memory reference control mechanism.
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Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Non-temporal memory reference control mechanism.
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Owens, Jeffrey Dean; Ma, Edward Tang K.; Loomis, Don; Chenot, Tom, Programmable and scalable microcontroller architecture.
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Arakawa, Fumio, RISC processor with instruction executing on different size operand and prefix instruction identifying select flag update for respective size.
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Henry, Glenn; Hooker, Rodney; Parks, Terry, Selective interrupt suppression.
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Henry, G. Glenn; Hooker, Rodney E.; Parks, Terry, Suppression of store checking.
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Henry,G. Glenn; Hooker,Rodney E.; Parks,Terry, Suppression of store checking.
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Christie, David S., System and method for controlling access to a privilege-partitioned address space with a fixed set of attributes.
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Owens, Jeffrey D.; Ma, Edward Tangkwai; Loomis, III, Donald W.; Chenot, Thomas Augustus, Transfer triggered microcontroller with orthogonal instruction set.
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Christie David S. ; Kranich Uwe,DEX, Transparent extended state save.
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Christie, David S.; McGrath, Kevin J., Uniform register addressing using prefix byte.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Microprocessor using an instruction field to expand the condition flags and a computer system employing the microprocess 원문보기

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Microprocessor using an instruction field to expand the condition flags and a computer system employing the microprocess 원문보기

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