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Electrically programmable antifuse incorporating dielectric and amorphous silicon interlayers

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/04
  • H01L-029/00
  • H01L-023/48
출원번호 US-0631191 (1996-04-11)
발명자 / 주소
  • McCollum John L.
  • Eltoukhy Abdelshafy A.
  • Forouhi Abdul Rahim
출원인 / 주소
  • Actel Corporation
대리인 / 주소
    D'Alessandro & Ritchie
인용정보 피인용 횟수 : 29  인용 특허 : 56

초록

An antifuse may be fabricated as a part of an integrated circuit in a layer located above and insulated from the semiconductor substrate. The antifuse includes a lower first metal electrode, a first antifuse dielectric layer, preferably silicon nitride, disposed on the lower first electrode and an a

대표청구항

[ What is claimed is:] [1.] An electrically programmable antifuse element disposed on a semiconductor substrate in an integrated circuit comprising:an insulating layer covering active circuit elements on said integrated circuit;a first metal electrode;a first dielectric layer disposed on said first

이 특허에 인용된 특허 (56)

  1. Hawley Frank W. (Campbell CA) Yeouchung Yen (San Jose CA), Above via metal-to-metal antifuse.
  2. Boardman William J. (San Jose CA) Chan David P. (San Ramon CA) Chang Kuang-Yeh (Los Gatos CA) Gabriel Calvin T. (Pacifica CA) Jain Vivek (Milpitas CA) Nariani Subhash R. (San Jose CA), Anti-fuse structures and methods for making same.
  3. Chen Kueing-Long (Plano TX) Shah Ashwin H. (Dallas TX) Liu David K. (Sunnyvale CA), Antifuse structure and method of fabrication.
  4. Zhang Guobiao (Elcerrito CA) Hu Chenming (Alamo CA) Chiang Steve S. (Saratoga CA), Antifuse structure suitable for VLSI application.
  5. Dixit Pankaj (San Jose CA), Antifuse with nonstoichiometric tin layer and method of manufacture thereof.
  6. Lowrey Tyler A. (Boise ID) Lee Ruojia (Boise ID), Array of read-only memory cells, eacch of which has a one-time, voltage-programmable antifuse element constructed within.
  7. Lytle Steven A. (Bethlehem PA), Buried antifuse.
  8. Freeman Ross H. (San Jose CA), Configurable electrical circuit having configurable logic elements and configurable interconnects.
  9. Hollingsworth Deems R. (Missouri City TX), Deep polysilicon emitter antifuse memory cell.
  10. Forouhi Abdul R. (San Jose CA) Hamdy Esmat Z. (Fremont CA) Hu Chenming (Alamo CA) McCollum John L. (Saratoga CA), Electrically programmable antifuse and fabrication processes.
  11. Husher John D. (Los Altos Hills CA) Forouhi Abdul R. (San Jose CA), Electrically programmable antifuse element.
  12. McCollum John L. (Saratoga CA) Chen Shih-Ou (Fremont CA), Electrically programmable antifuse element incorporating a dielectric and amorphous silicon interlayer.
  13. Forouhi Abdul R. (San Jose CA), Electrically programmable antifuse incorporating dielectric and amorphous silicon interlayer.
  14. McCollum John L. (Saratoga FL) Eltoukhy Abdelshafy A. (San Jose CA) Forouhi Abdul R. (San Jose CA), Electrically programmable antifuse incorporating dielectric and amorphous silicon interlayers.
  15. Gambino Jeffrey P. (Gaylordsville CT) Schepis Dominic J. (Wappingers Falls NY) Seshan Krishna (Beacon NY), Electrically programmable antifuse using metal penetration of a junction.
  16. Hamdy Esmat Z. (Fremont CA) Mohsen Amr M. (Saratoga CA) McCullum John L. (Saratoga CA), Electrically-programmable low-impedance anti-fuse element.
  17. Hamdy Esmat Z. (Fremont CA) Mohsen Amr M. (Saratoga CA) McCullum John L. (Saratoga CA) Chen Shih-Ou (Fremont CA) Chiang Steve S. (Saratoga CA), Electrically-programmable low-impedance anti-fuse element.
  18. Cox William D. (Milpitas CA), Field programmable antifuse device and programming method therefor.
  19. Magel Gregory A. (Dallas TX) Stoltz Richard A. (Plano TX), Fuse and antifuse reprogrammable link for integrated circuits.
  20. Whitten Ralph G. (San Jose CA), Fusible link structure for integrated circuits.
  21. Tamamura Masaya (Inagi JPX) Emori Shinji (Urawa JPX) Watanabe Yoshio (Kawasaki JPX) Shimotsuhama Isao (Kawasaki JPX), Gate array device having macro cells for forming master and slave cells of master-slave flip-flop circuit.
  22. Dixit Pankaj (San Jose CA) Ingram ; III William P. (Los Altos CA) Holzworth Monta R. (Santa Clara CA) Klein Richard (Mountain View CA), Improved method of fabricating antifuses in an integrated circuit device and resulting structure.
  23. Cohen Simon S. (Burlington MA), Incoherent radiation regulated voltage programmable link.
  24. Kwok Siang P. (Dallas TX) Wang Shoue-Jen (Plano TX), Limited metal reaction for contact cleaning and improved metal-to-metal antifuse contact cleaning method.
  25. McCollum John L. (Saratoga CA) Forouhi Abdul R. (San Jose CA), Low-temperature process metal-to-metal antifuse employing silicon link.
  26. Chen Wenn-Jei (1462 Saskatchewan Sunnyvale CA 94087) Chiang Steve S. (19937 Scotland Dr. Saratoga CA 95070) Hawley Frank W. (1360 Capri Dr. Campbell CA 95008), Metal-to-metal antifuse including etch stop layer.
  27. Tigelaar Howard L. (Allen TX) Misium George (Plano TX), Metal-to-metal antifuse structure.
  28. Spratt David B. (Plano TX) Chen Kueing-Long (Plano TX), Method and device for controlling current in a circuit.
  29. Pintchovski Faivel (Austin TX) Tobin Philip J. (Austin TX), Method for making a w/tin contact.
  30. Boardman William J. (San Jose CA) Chan David P. (San Ramon CA) Chang Kuang-Yeh (Los Gatos CA) Gabriel Calvin T. (Pacifica CA) Jain Vivek (Milpitas CA) Nariani Subhash R. (San Jose CA), Method for making anti-fuse structures.
  31. Boardman William J. (San Jose CA) Chan David P. (San Ramon CA) Chang Kuang-Yeh (Los Gatos CA) Gabriel Calvin T. (Pacifica CA) Jain Vivek (Milpitas CA) Nariani Subhash R. (San Jose CA), Method for making cusp-free anti-fuse structures.
  32. Hall Stacy W. (San Antonio TX) Delgado Miguel A. (San Antonio TX), Method for manufacturing anti-fuse structures.
  33. Roesner Bruce B. (Poway CA), Method for reducing resistance for programmed antifuse.
  34. Birkner John M. (Portola Valley CA) Martin David T. (Santa Clara CA) Wong Richard J. (Milpitas CA), Method of determining an electrical characteristic of an antifuse and apparatus therefor.
  35. Ellsworth Daniel L. (Fort Collins CO) Sullivan Paul A. (Fort Collins CO), Method of fabricating a high density, low power, merged vertical fuse/bipolar transistor.
  36. Tung Yingsheng (Plano TX) Montgomery Scott (Plano TX), Method of forming an antifuse.
  37. Bhushan Bharat (Santa Clara CA), Method of making a field programmable read only memory (ROM) cell using an amorphous silicon fuse with buried contact po.
  38. Cohen Simon S. (Burlington MA), Method of making electrically programmable link structures.
  39. El-Ayat Khaled A. (Palo Alto) Hayes Kenneth D. (San Jose) Speers Theodore M. (San Leandro) Bakker Gregory W. (Sunnyvale CA), Methods for preventing disturbance of antifuses during programming.
  40. Lowrey Tyler A. (Boise ID) Lee Ruojia (Boise ID), One-sided ozone TEOS spacer.
  41. Dixit Pankaj (San Jose CA) Holzworth Monta R. (Santa Clara CA) Klein Richard (Mountain View CA) Ingram ; III William P. (Los Altos CA), Plug contact with antifuse.
  42. Chiang David (Saratoga CA), Power management for programmable logic devices.
  43. Husher John D. (Los Altos Hills CA) Forouhi Abdul R. (San Jose CA), Process for fabricating electrically programmable antifuse element.
  44. Hsu Fu-Chieh (Saratoga CA) Pai Pei-Lin (Cupertino CA), Programmable antifuse structure, process, logic cell and architecture for programmable integrated circuits.
  45. Choi Kyu H. (Santa Clara CA), Programmable interconnect device and method of manufacturing same.
  46. Gordon Kathryn E. (Mountain View CA) Wong Richard J. (Milpitas CA), Programmable interconnect structures and programmable integrated circuits.
  47. Mohsen Amr M. (Saratoga CA) Hamdy Esmat Z. (Fremont CA) McCullum John L. (Saratoga CA), Programmable low impedance anti-fuse element.
  48. Hamdy Esmat Z. (Fremont CA) Mohsen Amr M. (Saratoga CA) McCullum John L. (Saratoga CA), Programmable low-impedance anti-fuse element.
  49. Tsang Wai M. (Beaverton OR) Hu Daniel C. (Los Altos Hills CA) Khong Dong T. (Singapore SGX), Programmable semiconductor antifuse structure and method of fabricating.
  50. Tsang Wai M. (Beaverton OR) Hu Daniel C. (Los Altos Hills CA) Khong Dong T. (Singapore SGX), Programmable semiconductor antifuse structure and method of fabricating.
  51. Gordon Kathryn E. (Mountain View CA) Chan Andrew K. (Palo Alto CA), Programming of antifuses.
  52. Favreau David P. (Coopersburg PA), Self-aligned vertical antifuse.
  53. Gordon Kathryn E. (Palo Alto CA) Jenq Ching S. (San Jose CA), Semiconductor antifuse structure and method.
  54. Cohen Simon S. (Burlington MA) Raffel Jack I. (Lexington MA), Voltage programmable links programmed with low current transistors.
  55. Stopper Herbert (Orchard Lake MI) Perkins Cornelius C. (Brimingham MI), Wafer and method of making same.
  56. Delgado Miguel A. (San Antonio TX) Hall Stacy W. (San Antonio TX), Wet/dry anti-fuse via etch.

이 특허를 인용한 특허 (29)

  1. Bulovic, Vladimir; Mandell, Aaron; Perlman, Andrew, Addressable and electrically reversible memory switch.
  2. Zhang Guobiao ; Hu Chenming ; Chiang Steve S., Antifuse structure suitable for VLSI application.
  3. Kishore K. Chakravorty, Capacitor with defect isolation and bypass.
  4. Hecht, Volker, Circuits and methods for preventing over-programming of ReRAM-based memory cells.
  5. Radens, Carl J.; Brintzinger, Axel C., Dual damascene anti-fuse with via before wire.
  6. Mandell, Aaron; Perlman, Andrew, Floating gate memory device using composite molecular material.
  7. Greene, Jonathan; Hawley, Frank; McCollum, John, Front to back resistive random access memory cells.
  8. McCollum, John L.; Hamdy, Esmat Z., Low leakage ReRAM FPGA configuration cell.
  9. Krieger, Juri H.; Yudanov, Nikolai, Memory device.
  10. Krieger, Juri H.; Yudanov, Nikolai, Memory device.
  11. Krieger, Juri H.; Yudanov, Nikolai, Memory device.
  12. Krieger, Juri H.; Yudanoy, Nikolai, Memory device.
  13. Krieger, Juri H.; Yudanov, N. F., Memory device with a self-assembled polymer film and method of making the same.
  14. Krieger, Juri H.; Yudanov, Nikolai, Memory device with active and passive layers.
  15. Krieger, Juri H.; Yudanov, Nikolai, Memory device with active passive layers.
  16. Matthias Lehr DE; Wolfgang Leiberg DE, Method for fabricating a wiring plane on a semiconductor chip with an antifuse.
  17. Lin Yei-Hsiung,TWX ; Huang Chih-Chun,TWX ; Lin Chen-Bin,TWX ; Chung Cheng-Hui,TWX, Method of fabricating crack resistant inter-layer dielectric for a salicide process.
  18. Preusse, Axel; Friedemann, Michael; Seidel, Robert; Freudenberg, Berit, Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime.
  19. Krieger, Juri H.; Yudanov, Nikolay F., Molecular memory cell.
  20. Krieger,Juri H; Yudanov,Nicolay F, Molecular memory cell.
  21. Bulovic, Vladimir; Mandell, Aaron; Perlman, Andrew, Molecular memory device.
  22. Kingsborough,Richard P.; Sokolik,Igor, Organic thin film Zener diodes.
  23. Lan James J. D. ; Chiang Steve S. ; Shepherd William H. ; Wu Paul Y. F., Programmable/reprogrammable structure using fuses and antifuses.
  24. Hawley Frank W. ; McCollum John L. ; Go Ying ; Eltoukhy Abdelshafy, Raised tungsten plug antifuse and fabrication processes.
  25. McCollum John L. ; Hawley Frank W., Reduced leakage antifuse structure.
  26. Bulovic, Vladimir; Mandell, Aaron; Perlman, Andrew, Reversible field-programmable electric interconnects.
  27. Bulovic,Vladimir; Mandell,Aaron; Perlman,Andrew, Reversible field-programmable electric interconnects.
  28. Noda, Kosei; Yasumoto, Seiji; Yoshizumi, Kensuke; Miyamoto, Toshiyuki, Semiconductor device and manufacturing method thereof.
  29. Tamura Yoshimitsu,JPX ; Nasu Takumi,JPX ; Fukuhara Hideyuki,JPX ; Numaga Shigeki,JPX, Semiconductor memory device with antifuse.
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