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An integrated CPU has an on-board switching voltage regulator with an electrically-erasable programmable read-only memory electronically accessible for storing a feedback reference coefficient for control. In further embodiments, output voltage is tuned via a second EEPROM storing an electronically

An integrated CPU has an on-board switching voltage regulator with an electrically-erasable programmable read-only memory electronically accessible for storing a feedback reference coefficient for control. In further embodiments, output voltage is tuned via a second EEPROM storing an electronically accessible value in concert with a solid-state resistor ladder. In other embodiments, signals on interrupt lines to the CPU are monitored to provide a prewarning of impending activity by the CPU requiring dramatically increased current flow. In yet other embodiments, solid state circuitry is provided to reduce or eliminate capacitors used for dealing with input current surges to the CPU.

대표청구항 ▼

[ What is claimed is:] [2.] A voltage-regulated, single chip, microprocessor-based CPU for a general-purpose computer, comprising:a CPU portion;a switching voltage regulator portion having a primary input and a regulated output connected to the CPU portion; anda wakeup logic circuit coupled to inter

[ What is claimed is:] [2.] A voltage-regulated, single chip, microprocessor-based CPU for a general-purpose computer, comprising:a CPU portion;a switching voltage regulator portion having a primary input and a regulated output connected to the CPU portion; anda wakeup logic circuit coupled to interrupt lines coupled to the CPU portion and to the voltage regulator portion, wherein interrupt activity is signaled to the voltage regulator portionwherein the switching voltage regulator portion comprises:switching circuitry including a buck converter connected between the primary input and the regulated output, for altering voltage at the regulated output; andadjustment circuitry including an electrically erasable programmable read-only memory (EEPROM), the adjustment circuitry connected to the switching circuitry and to the regulated output;wherein the adjustment circuitry controls the switching circuitry to provide a voltage magnitude at the regulated output according to a value stored in the EEPROM, and wherein the wakeup logic circuit controls a divided CPU clock connected to the CPU and to the buck converter.