초록 ▼

A semiconductor memory device achieves high speed operation while operating at a low power supply voltage by boosting the voltage level at the plate node of a memory cell during an access operation. The memory device includes a plate voltage generator which generates a variable voltage level. The pl

A semiconductor memory device achieves high speed operation while operating at a low power supply voltage by boosting the voltage level at the plate node of a memory cell during an access operation. The memory device includes a plate voltage generator which generates a variable voltage level. The plate voltage generator includes a pair of switches for coupling the plate node to either a conventional (1/2)VCC voltage generator or a power supply node in response to a control signal. The plate voltage generator also includes a pulse generator that generates a pulse signal for controlling the switches in response to the control signal. During a precharge period, the bitline pair is charged to VCC. The plate voltage generator charges the plate node to (1/2)VCC during the precharge state and then to VCC during an access operation. This boosts the voltage level at the storage node of the memory cell, thereby decreasing the time required to amplify the signals on the bitlines.

대표청구항 ▼

[ We claim:] [1.] A semiconductor memory device comprising:a memory cell having a plate node; anda plate voltage generator coupled to the plate node, the plate voltage generator generating a first voltage signal at the plate node during a precharge operation and a second voltage signal at the plate

[ We claim:] [1.] A semiconductor memory device comprising:a memory cell having a plate node; anda plate voltage generator coupled to the plate node, the plate voltage generator generating a first voltage signal at the plate node during a precharge operation and a second voltage signal at the plate node during an access operation and before a sensing operation.