초록 ▼

A bit-phase aligning circuit includes a bit-phase adjusting circuit and a synchronizing pattern detection circuit. The bit-phase adjusting circuit adjusts a phase difference between a data signal and a clock signal by adjusting a delay amount of the data signal based on a determination result signal

A bit-phase aligning circuit includes a bit-phase adjusting circuit and a synchronizing pattern detection circuit. The bit-phase adjusting circuit adjusts a phase difference between a data signal and a clock signal by adjusting a delay amount of the data signal based on a determination result signal from the synchronizing pattern detection circuit. In the synchronizing pattern detection circuit, the data signal is sampled using the clock signal so as to detect a synchronizing pattern inserted in the data signal. When the synchronizing pattern is detected, the synchronizing pattern detection circuit determines that a phase relationship between the data signal and the clock signal is proper. On the other hand, when not detected, the synchronizing pattern detection circuit determines the phase relationship therebetween to be improper. This determination result signal is fed to the bit-phase adjusting circuit where the phase difference between the data signal and the clock signal is adjusted.

대표청구항 ▼

[ What is claimed is:] [8.] A bit-phase alignment circuit, comprising:a bit-phase adjusting circuit for receiving input data containing therein a synchronizing pattern, adjusting a bit-phase difference between the input data and an input clock, and generating adjusted input data having the adjusted

[ What is claimed is:] [8.] A bit-phase alignment circuit, comprising:a bit-phase adjusting circuit for receiving input data containing therein a synchronizing pattern, adjusting a bit-phase difference between the input data and an input clock, and generating adjusted input data having the adjusted bit-phase difference; anda synchronizing pattern detection circuit for receiving the adjusted input data, for detecting the synchronizing pattern in the adjusted input data, determining whether a phase relationship between the adjusted input data and the input clock is proper or improper based on whether the synchronizing pattern is detected or not, and generating a determination result signal to the bit-phase adjusting circuit for controlling the bit-phase adjusting circuit to re-adjust the bit-phase difference based on the determination result signal.