초록 ▼

In accordance with the present invention, a programmable array includes hierarchical configuration and state storage. The array comprises an active storage for an active configuration and an active state as well as an inactive storage for one or more inactive configurations and one or more inactive

In accordance with the present invention, a programmable array includes hierarchical configuration and state storage. The array comprises an active storage for an active configuration and an active state as well as an inactive storage for one or more inactive configurations and one or more inactive states. The array further comprises logic and routing configured by the active configuration. The logic includes a plurality of combinational elements and a plurality of sequential logic elements for providing the states. Bits are transferred between the active and the inactive storage. The inactive storage is accessible for read or write operations by the active configuration by a structure comprising: a core including a plurality of configurable elements selectively coupled to each other, a memory controller for controlling the memory that configures the logic and routing in accordance with the active configuration, a command register to hold commands for the memory controller, a memory address register to address the memory, and a memory data register coupled to the memory and the plurality of combinational elements. In one embodiment, the array of the present invention includes a configurable routing structure for providing the active configuration access to the memory address register, the memory data register, and the command register. The configurable routing structure is generally controlled by signals from the user logic, thereby significantly increasing user flexibility in using the programmable array.

대표청구항 ▼

[ We claim:] [1.] A programmable logic device with hierarchical configuration and state storage on an integrated chip, comprising:an active storage for an active configuration and an active state;an inactive storage for one or more inactive configurations and one or more inactive states;logic and ro

[ We claim:] [1.] A programmable logic device with hierarchical configuration and state storage on an integrated chip, comprising:an active storage for an active configuration and an active state;an inactive storage for one or more inactive configurations and one or more inactive states;logic and routing configured by the active configuration, wherein the logic includes a plurality of combinational elements and a plurality of sequential logic elements for providing the states; andmeans to transfer the bits between active and inactive storage.