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Compliant bump technology 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/60
출원번호 US-0826606 (1997-04-03)
발명자 / 주소
  • Canning Everett Joseph
  • Finley Donald W.
  • Hoppes Charles K.
  • Sheridan Michael
출원인 / 주소
  • Lucent Technologies Inc.
인용정보 피인용 횟수 : 59  인용 특허 : 4

초록

The specification describes an interconnection technique using compliant metal coated photodefined polymer bumps for mounting and interconnecting component assemblies on substrates such as glass, printed wiring boards, etc. The polymer chosen for the bump structure has a relatively low T.sub.g and t

대표청구항

[ We claim:] [1.] Method for bonding two elements together, said two elements consisting of an electrical or photonic component and a substrate for supporting said component, the method comprising the steps of:a. forming a plurality of bonding pad on the first of said elements,b. depositing a layer

이 특허에 인용된 특허 (4)

  1. Chang Shyh-Ming (Hsinchu TWX) Lee Yu-Chi (Taipei Hsien TWX) Tang Pao-Yun (Hsinchu TWX), Connection construction and method of manufacturing the same.
  2. Bull David N. (Brockport NY), Method for precision multichip assembly.
  3. Brown Paula J. (Cream Ridge NJ) Fang Treliant (Lawrenceville NJ) Ors Jose A. (New Hope PA) Raju Venkataram R. (New Providence NJ) Shah Akshay V. (Londonberry NH), Method of making circuit devices comprising a dielectric layer of siloxane-caprolactone.
  4. Christie Frederick Richard (Endicott NY) Papathomas Kostas I. (Endicott NY) Wang David Wei (Vestal NY), Solder interconnection structure and process for making.

이 특허를 인용한 특허 (59)

  1. Tatsuzawa, Takashi; Watanabe, Itsuo; Fukushima, Naoki; Kume, Masahide, Adhesive film for circuit connection, and circuit connection structure.
  2. Tatsuzawa, Takashi; Watanabe, Itsuo; Fukushima, Naoki; Kume, Masahide, Adhesive film for circuit connection, and circuit connection structure.
  3. Brintzinger, Axel, Arrangement for the protection of three-dimensional structures on wafers.
  4. Lake, Rickie C., Battery powerable apparatus, radio frequency communication device, and electric circuit.
  5. Kwon, Yonghwan; Lee, Chungsun; Kang, Sayoon, Bump structure for a semiconductor device and method of manufacture.
  6. Ding, Yi-Chuan; Lee, Xin Hui; Chen, Kun-Ching, Chip scale package and manufacturing method.
  7. Lu,Su Tsai, Chip structure and chip package structure.
  8. Lu, Su-Tsai; Chen, Tai-Hong, Electronic assembly having a multilayer adhesive structure.
  9. Deppisch, Carl L.; Houle, Sabina J.; Fitzgerald, Thomas J.; Dayton, Kristopher E.; Hua, Fay, Electronic assembly having a wetting layer on a thermally conductive heat spreader.
  10. Dishongh, Terrance J.; Churilla, Paul W.; Pullen, David H., Electronic assembly having an indium thermal couple.
  11. Hashimoto, Nobuaki, Electronic board and manufacturing method thereof, electro-optical device, and electronic apparatus.
  12. Tuttle, Mark E., Electronic communication devices, methods of forming electrical communication devices, and communications methods.
  13. Gebauer, Uta; Hedler, Harry; H?gerl, J?rgen; Strutz, Volker, Electronic component with a semiconductor chip and method for producing the electronic component.
  14. Hauser, Christian; Reiss, Martin, Electronic component with a semiconductor chip, and method of producing the electronic component.
  15. Hedler, Harry; Meyer, Thorsten, Electronic component with at least one semiconductor chip and method for producing the electronic component.
  16. Haimerl,Alfred; Hedler,Harry; Pohl,Jens, Electronic component with flexible contacting pads and method for producing the electronic component.
  17. Hedler, Harry; Meyer, Thorsten; Vasquez, Barbara, Electronic structure.
  18. Richard H. Estes ; James E. Clayton ; Koji Ito JP; Masanori Akita JP; Toshihiro Mori JP; Minoru Wada JP, Flip chip mounting technique.
  19. Tanaka, Toshiaki; Kaneko, Hiroki; Hiyama, Ikuo, Illuminating apparatus and display apparatus using the same.
  20. Hsu, Yung Yu; Liau, Shyi Ching; Tain, Ra Min; Jeng, Jr Yuan, Interconnect structure with stress buffering ability and the manufacturing method thereof.
  21. Hsu, Yung-Yu; Liau, Shyi-Ching; Tain, Ra-Min; Jeng, Jr-Yuan, Interconnect structure with stress buffering ability and the manufacturing method thereof.
  22. Lay, Ming-Yi; Hsieh, Yong-Fen; Tsai, Shang-Kung; Lo, Chin-Kun, Metal bump with an insulating sidewall and method of fabricating thereof.
  23. Lay,Ming Yi; Hsieh,Yong Fen; Tsai,Shang Kung; Lo,Chin Kun, Metal bump with an insulating sidewall and method of fabricating thereof.
  24. Chang, Shyh-Ming; Jou, Jwo-Huei; Wu, Chi-Yuan, Method for bonding IC chips having multi-layered bumps with corrugated surfaces and devices formed.
  25. Hedler, Harry; Irsigler, Roland; Pohl, Jens, Method for connecting circuit devices.
  26. Oppermann, Hermann, Method for connecting two joining surfaces.
  27. Hsuan,Min Chih; Chen,Paul; Liu,Hermen; Wang,Kun Chih; Ho,Kai Kuang, Method for manufacturing wafer level chip scale package structure.
  28. Tanaka, Shuichi, Method for mounting semiconductor device.
  29. Ito, Masahiko; Masuko, Daisuke, Method for producing an anisotropic conductive film.
  30. Frankowsky, Gerd; Meyer, Thorsten, Method of attaching semiconductor devices on a switching device and such an attached device.
  31. Lake, Rickie C., Method of conductively interconnecting electronic components, battery powerable apparatus, radio frequency communication device, and electric circuit.
  32. Terrance J. Dishongh ; Paul W. Churilla ; David H. Pullen, Method of constructing an electronic assembly having an indium thermal couple and an electronic assembly having an indium thermal couple.
  33. Kinoshita Makoto,JPX, Method of forming bump electrodes.
  34. Hedler, Harry; Haimerl, Alfred, Method of producing an electronic component with flexible bonding.
  35. Kazuhisa Tsunoi JP; Hidehiko Kira JP; Shunji Baba JP; Akira Fujii JP; Toshihiro Kusagaya JP; Kenji Kobae JP; Norio Kainuma JP; Naoki Ishikawa JP; Satoshi Emoto JP, Mounting method of semiconductor device.
  36. Tsunoi, Kazuhisa; Kira, Hidehiko; Baba, Shunji; Fujii, Akira; Kusagaya, Toshihiro; Kobae, Kenji; Kainuma, Norio; Ishikawa, Naoki; Emoto, Satoshi, Mounting method of semiconductor device.
  37. Hashimoto, Nobuaki, Mounting structure of electronic component.
  38. Kaneko,Ken, Mounting structure, electro-optical device, and electronic apparatus.
  39. McFarland, Jonathan; Raj, Kannan, Optical and electrical interconnect.
  40. McFarland,Jonathan; Raj,Kannan, Optical and electrical interconnect.
  41. Kim, Eun Ah, Organic light emitting display (OLED) with conductive spacer and its method of manufacture.
  42. Sun, Joseph; Cheng, Kuang-Chih; Chen, Ming-Chieh; Lee, Kevin; Pan, Jui-Hsiang, Package of a semiconductor device with a flexible wiring substrate and method for the same.
  43. Nakata Yoshikazu,JPX ; Otomo Syozo,JPX ; Tanaka Kazunari,JPX ; Uno Koichi,JPX, Process for forming fine thick-film conductor patterns.
  44. Tuttle, John R., Radio frequency identification device and method.
  45. Tuttle, John R., Radio frequency identification device and method.
  46. Nishi, Kazuo; Adachi, Hiroki; Kusumoto, Naoto; Sugawara, Yuusuke; Takahashi, Hidekazu; Yamada, Daiki; Hiura, Yoshikazu, Semiconductor device and method for manufacturing the same.
  47. Hashimoto, Nobuaki, Semiconductor device and method of manufacture thereof, circuit board and electronic instrument.
  48. Hasimoto,Nobuaki, Semiconductor device and method of manufacture thereof, circuit board and electronic instrument.
  49. Hashimoto,Nobuaki, Semiconductor device, circuit board and electronic instrument that include an adhesive with conductive particles therein.
  50. Vittu, Julien, Semiconductor package fabrication process and semiconductor package.
  51. Belke ; Jr. Robert Edward ; Hayden Brian John ; Pham Cuong Van ; Nuno Rosa Lynda ; Todd Michael George, Solderless flip-chip assembly and method and material for same.
  52. Sengupta, Dipak; Goida, Thomas, Stress free package and laminate-based isolator package.
  53. Jacobs Elizabeth G. ; Heinen Katherine G., Stress relief matrix for integrated circuit packaging.
  54. Raj, Pulugurtha Markondeya; Kumbhat, Nitesh; Sundaram, Venkatesh V.; Tummala, Rao R.; Qin, Xian, Stress relieving second level interconnect structures and methods of making the same.
  55. Ho,Yiu Sing; Lu,Guo Hong; Chen,Can Hua; Luo,Yuan Neng; Wang,Jeffrey L.; Zhang,Liu Jun, System and method for improving hard drive actuator lead attachment.
  56. Tuttle, John R., System and method to track articles at a point of origin and at a point of destination using RFID.
  57. Eskridge, Mark, Systems and methods for platinum ball bonding.
  58. Collins, Andrew; Cheng, Chih-Min, Thermal interface material.
  59. Lake,Rickie C., Thin profile battery bonding method, method of conductively interconnecting electronic components, battery powerable apparatus, radio frequency communication device, and electric circuit.
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