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Extended bond pads with a plurality of perforations 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-029/54
  • H01L-023/485
출원번호 US-0716134 (1996-09-20)
발명자 / 주소
  • Galloway Terry R.
출원인 / 주소
  • Integrated Device Technology, Inc.
대리인 / 주소
    Majestic, Parsons, Siebert & Hsue
인용정보 피인용 횟수 : 52  인용 특허 : 17

초록

Extension areas of a metal layer electrically connected to the original die bond pad allow for testing connections to be made. In this way, the connection area used for the final packaging of the die will not be damaged. The extension areas can be removed along with the testing connections. The use

대표청구항

[ What is claimed is:] [1.] A structure comprising:a die;a wire bond pad on the die;a passivation layer over a portion of the die; anda metal layer on the die and electrically connected to the wire bond pad and extending over a portion of the passivation layer, the metal layer including an extension

이 특허에 인용된 특허 (17)

  1. Bergeron Richard J. (Essex Junction VT) LaMothe Thomas J. (Georgia VT) Suarez Joseph E. (Burlington VT) Thompson John A. (Monkton Ridge VT), Additive structure and method for testing semiconductor wire bond dies.
  2. Baker Thomas R. (Tempe AZ) Anderson George F. (Tempe AZ), Bonding pad for semiconductor devices.
  3. Ruben Paul L. (Penfield NY), Compact small format zoom lens.
  4. Golshan Shahin (Midland TX) St. Martin Craig A. (Midland TX) Rhodine Craig W. (Midland TX), Configuration and method for positioning semiconductor device bond pads using additional process layers.
  5. Albergo Christopher J. (Penfield NY) Reele Samuel (Rochester NY), Electrode structure for light emitting diode array chip.
  6. Cusack Michael D. (Monument CO) Hagen Michael P. (Colorado Springs CO) Larkin James E. (Colorado Springs CO), Integrated circuit having an improved bond pad.
  7. Kierse Oliver J. (Clare County IEX), Integrated circuit package with improved heat dissipation.
  8. Farnworth Warren (Nampa ID) Wood Alan (Boise ID), Method and apparatus for manufacturing known good semiconductor die.
  9. Akram Salman (Boise ID) Farnworth Warren M. (Nampa ID) Wood Alan G. (Boise ID), Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice.
  10. Baker Mark H. (San Jose CA), Method for forming solder bumps in semiconductor devices.
  11. Kumar Nalin (Austin TX) Goruganthu Rama R. (Austin TX) Ghazi Mohammed K. (Austin TX), Method of making semiconductor bonding bumps using metal cluster ion deposition.
  12. Garcia Enrique (Sandy Hook CT), Semiconductor chip with recessed bond pads.
  13. Hosomi Eiichi (Kawasaki JPX) Takubo Chiaki (Yokohama JPX) Tazawa Hiroshi (Ichikawa JPX) Miyamoto Ryouichi (Kawasaki JPX) Arai Takashi (Oita JPX) Shibasaki Koji (Kawasaki JPX), Semiconductor device comprising fine bump electrode having small side etch portion and stable characteristics.
  14. Okumura Tomisaburo (Kyoto JA) Matsuo Takatoshi (Kyoto JA), Semiconductor device having bonding pads extending over active regions.
  15. Mizushima Kazuyuki (Tokyo JPX), Semiconductor device with an electrode pad having increased mechanical strength.
  16. Oku Kazutoshi (Hyogo JPX) Hirosue Masahiro (Hyogo JPX), Semiconductor device with an elevated bonding pad.
  17. Lam Ken (Colorado Springs CO), TAB testing of area array interconnected chips.

이 특허를 인용한 특허 (52)

  1. Spory, Erick Merle, 3D printed hermetic package assembly and method.
  2. Lee, Jin-Yuan; Lo, Hsin-Jung, Chip assembly with interconnection by metal bump.
  3. Kirk,Gregory L.; Brown,Matthew; Ostuni,Emanuele; Kim,Enoch; Aumond,Bernardo D.; Schueller,Olivier; Sweetnam,Paul; Benoit,Brian, Device for monitoring haptotaxis.
  4. Spory, Erick Merle, Environmental hardened packaged integrated circuit.
  5. Spory, Erick Merle, Environmental hardening integrated circuit method and apparatus.
  6. Seshan,Krishna; Jeng,Kevin; Dun,Haiping, Forming a cap above a metal layer.
  7. Paul Davis Bell, Integrated circuit having wirebond pads suitable for probing.
  8. Carichner Karla Y., Integrated circuit package having bond fingers with alternate bonding areas.
  9. Spory, Erick Merle, Integrated circuit with printed bond connections.
  10. Danziger Steve M ; Shah Tushar, Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects.
  11. Danziger, Steve M.; Shah, Tushar, Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects.
  12. Danziger, Steve M; Shah, Tushar, Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects.
  13. Spory, Erick Merle, Method and apparatus for printing integrated circuit bond connections.
  14. Rincon Reynaldo M. ; U Yee Hsun, Method for maximizing interconnection integrity and reliability between integrated circuits and external connections.
  15. Spory, Erick Merle, Method for remapping a packaged extracted die.
  16. Spory, Erick Merle, Method for remapping a packaged extracted die with 3D printed bond connections.
  17. Wolfgang Pahl DE; Alois Stelzl DE; Hans Kruger DE, Method of producing a surface acoustic wave component.
  18. Akram, Salman, Methods of fabricating semiconductor substrate-based BGA interconnection.
  19. Akram, Salman, Methods of fabricating semiconductor substrate-based BGA interconnections.
  20. Gay, Laurent; Guyader, Francois; Diette, Frederic, Microelectronic chip, component containing such a chip and manufacturing method.
  21. Chen, Sheng-Hsiung; Chen, Shun Long; Lin, Hungtse, Modified pad for copper/low-k.
  22. Li,Yuan, Pad structures to improve board-level reliability of solder-on-pad BGA structures.
  23. Anthony K. Stamper ; Sally J. Yankee, Recessed bond pad.
  24. Anthony K. Stamper ; Sally J. Yankee, Recessed bond pad.
  25. Stamper, Anthony K.; Yankee, Sally J., Recessed bond pad.
  26. Spory, Erick Merle, Remapped packaged extracted die.
  27. Spory, Erick Merle, Remapped packaged extracted die with 3D printed bond connections.
  28. Spory, Erick Merle; Barry, Timothy Mark, Repackaged integrated circuit and assembly method.
  29. Spory, Erick Merle; Barry, Timothy Mark, Repackaged integrated circuit assembly method.
  30. Spory, Erick Merle, Repackaged reconditioned die method and assembly.
  31. John MacPherson, Sacrificial bond pads for laser configured integrated circuits.
  32. Lin, Mou-Shiung; Lee, Jin-Yuan, Semiconductor chip structure.
  33. Hatano, Masaaki; Usui, Takamasa, Semiconductor device.
  34. Umehara, Norito; Umeda, Yoshikatsu, Semiconductor device and method of manufacturing same.
  35. Downey, Susan H.; Harper, Peter R.; Hess, Kevin; Leoni, Michael V.; Tran, Tu-Anh, Semiconductor device having a bond pad and method therefor.
  36. Yong,Lois E.; Harper,Peter R.; Tran,Tu Anh; Metz,Jeffrey W.; Leal,George R.; Van Dinh,Dieu, Semiconductor device having a bond pad and method therefor.
  37. Hiraga Noriaki,JPX, Semiconductor integrated circuit device.
  38. Akram, Salman, Semiconductor substrate-based BGA interconnection.
  39. Akram,Salman, Semiconductor substrate-based BGA interconnection for testing semiconductor devices.
  40. Akram,Salman, Semiconductor substrate-based interconnection assembly for semiconductor device bearing external connection elements.
  41. Ertle, Werner; Goller, Bernd; Horn, Michael; Kothe, Bernd, Semiconductor wafer with electrically connected contact and test areas.
  42. Werner, Ertle; Goller, Bernd; Horn, Michael; Kothe, Bernd, Semiconductor wafer with electrically connected contact and test areas.
  43. Paul Davis Bell, Structure and method for probing wiring bond pads.
  44. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  45. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  46. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  47. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  48. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  49. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  50. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  51. Lin, Mou-Shiung; Chen, Michael; Chou, Chien-Kang; Chou, Mark, Wirebond pad for semiconductor chip or wafer.
  52. Lin,Mou Shiung; Chen,Michael; Chou,Chien Kang; Chou,Mark, Wirebond pad for semiconductor chip or wafer.
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