초록 ▼

In a decoding processing circuit of a digital signal receiver, a first comparison circuit detects that a prefix of packet data is inputted in a shift register on the basis of a count value of a counter circuit. In response to the result of detection, a pseudo-random binary sequence generation circui

In a decoding processing circuit of a digital signal receiver, a first comparison circuit detects that a prefix of packet data is inputted in a shift register on the basis of a count value of a counter circuit. In response to the result of detection, a pseudo-random binary sequence generation circuit outputs a pseudo-random binary sequence on the basis of a data group number and a data packet number outputted from the shift register and key data previously extracted by a key data fetch circuit. When a second comparison circuit detects that block data in the data packet is inputted in the shift register, an exclusive OR circuit exclusively ORs the pseudo-random binary sequence with receive data, so that decoded data is inputted in the shift register.

대표청구항 ▼

[ What is claimed is:] [1.] A digital signal receiver for receiving transmit data, in a communication system for transmitting said transmit data comprising a plurality of packets each having a second prescribed bit length, each packet including encoded information data of a first prescribed bit leng

[ What is claimed is:] [1.] A digital signal receiver for receiving transmit data, in a communication system for transmitting said transmit data comprising a plurality of packets each having a second prescribed bit length, each packet including encoded information data of a first prescribed bit length being divided into a plurality of blocks, each said packet including a plurality of specific data indicating the attributes of said packet and said encoded information data in first and second areas respectively, said digital signal receiver comprising:demodulation means for receiving transmitted said transmit data and demodulating the same to a corresponding digital signal;key data fetch means for receiving an output of said demodulation means and extracting master key data from a prescribed said packet among said plurality of packets including said encoded information data;decoding processing means for performing decoding processing on said encoded information data for every corresponding said packet on the basis of at least one specific data being included in every said packet and said master key data; anddata operation means for receiving an output of said decoding processing means and extracting said divided information data from said plurality of packets for structuring and outputting the same as said information data.