초록 ▼

An architecture for information processing devices which allows the construction of low cost, high performance systems for specialized computing applications involving sensor data processing. The reconfigurable processor architecture of the invention uses a programmable logic structure called an Ada

An architecture for information processing devices which allows the construction of low cost, high performance systems for specialized computing applications involving sensor data processing. The reconfigurable processor architecture of the invention uses a programmable logic structure called an Adaptive Logic Processor (ALP). This structure is similar to an extendible field programmable gate array (FPGA) and is optimized for the implementation of program specific pipeline functions, where the function may be changed any number of times during the progress of a computation. A Reconfigurable Pipeline Instruction Control (RPIC) unit is used for loading the pipeline functions into the ALP during the configuration process and coordinating the operations of the ALP with other information processing structures, such as memory, I/O devices, and arithmetic processing units. Multiple components having the reconfigurable architecture of the present invention may be combined to produce high performance parallel processing systems based on the Single Instruction Multiple Data (SIMD) architecture concept.

대표청구항 ▼

[ I claim:] [1.] A reconfigurable computing component, comprising the elements of:an adaptive logic processor, the adaptive logic processor further comprisinga plurality of individually configurable logic cells, the logic cells arranged in an array that includes a plurality of vertical columns of co

[ I claim:] [1.] A reconfigurable computing component, comprising the elements of:an adaptive logic processor, the adaptive logic processor further comprisinga plurality of individually configurable logic cells, the logic cells arranged in an array that includes a plurality of vertical columns of configurable logic cells and a plurality of horizontal rows of configurable logic cells; anda set of control lines for transmission of control signals and a set of data lines for transmission of data between a pipeline segment and a logic cell reconfiguration controller, the pipeline segment including a set of configured logic cells and positioned along the vertical extent of the array, wherein the set of control lines and the set of data lines extend across a plurality of columns of the array, thereby allowing the pipeline segment to be located at a plurality of horizontal locations of the array; anda logic cell reconfiguration controller for controlling configuration of the logic cells to form the pipeline segment and execution of the set of logical functions by the configured logic cells by transmitting instructions and data by means of the control signal lines and data lines.