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Semiconductor cap 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/12
  • H01L-023/48
출원번호 US-0576104 (1995-12-21)
발명자 / 주소
  • Gross Larry D.
  • Cadovius Richard W.,CAX
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Soucar
인용정보 피인용 횟수 : 33  인용 특허 : 8

초록

A method for manufacturing a cap for use in a semiconductor package is disclosed. The semiconductor package includes a semiconductor chip and a substrate. The chip is mounted with the substrate at a chip locus. The method preferably comprises the steps of placing a slug in a die, and exercising the

대표청구항

[ We claim:] [1.] A method for manufacturing a cap for use in a semiconductor package; said semiconductor package including a semiconductor chip and a substrate; said chip being mounted with said substrate; the method comprising the steps of:placing a slug in a die;exercising said die to cold flow s

이 특허에 인용된 특허 (8)

  1. Mahulikar Deepak (Meriden CT) Popplewell James M. (Guilford CT), Aluminum alloy semiconductor packages.
  2. Schurmann Heinz P. (421 Abington Ave. Mississauga CAX L5A 1L6), Cold flow forming.
  3. Hubbell Henry (Southington CT), Method and apparatus for making an eccentric locking collar.
  4. Hamilton ; C. Howard ; Ascani ; Leonard A., Method of making a metallic structure by combined superplastic forming and forging.
  5. Kurokawa Yasuhiro (Tokyo JPX), Package for semiconductor elements having thermal dissipation means.
  6. Ishida Yoshihiro (Tokorozawa JPX) Komatsu Katsuji (Kawagoe JPX) Mimura Seiichi (Kawagoe JPX) Takenouchi Kikuo (Higashimurayama JPX) Yabe Isao (Tokorozawa JPX) Ichikawa Shingo (Sayama JPX) Shimada Yos, Resin encapsulated pin grid array and method of manufacturing the same.
  7. Ommen Denise M. (Phoenix AZ) Tsai Chi-Taou (Chandler AZ) Baird John (Scottsdale AZ), Semiconductor package capable of spreading heat.
  8. Leach Almon E. (Lockport NY) Dietrich Frank J. (Tonawanda NY) Morris James P. (Amherst NY), Sheet forming method and apparatus.

이 특허를 인용한 특허 (33)

  1. Sherif Raed ; Toy Hilton T. ; Womac David J., Chip assembly with load-bearing lid in thermal contact with the chip.
  2. Kim, Tae Jun; Song, Yoo Sun, Chip on board package for optical mice and lens cover for the same.
  3. Okajima, Yusaku; Saido, Shuhei; Urushihara, Mika, Cover of seal cap for reaction chamber of semiconductor.
  4. Shishido Itsuroh,JPX ; Matsumoto Toshihiro,JPX, Electronic package with bonded structure and method of making.
  5. Shishido, Itsuroh; Matsumoto, Toshihiro, Electronic package with bonded structure and method of making.
  6. Wang Hsing-Seng,TWX, Flip chip chip-scale package.
  7. Polese Frank J. ; Rubin Jack A. ; Singer Michael J. ; Chichra Walter V. ; Grodio Anthony P. ; Ocher Vlad ; Escalante Henry ; Dixon William ; Rose David L. ; Weinshanker Stuart, Heat-dissipating aluminum silicon carbide composite manufacturing method.
  8. Djekic, Ognjen, Heatsinking and packaging of integrated circuit chips.
  9. Lischner David ; Nika Raymond J. ; Ronemus James Robert, Heatspreader for a flip chip device, and method for connecting the heatspreader.
  10. Lischner, David; Nika, Raymond J.; Ronemus, James Robert, Heatspreader for a flip chip device, and method for connecting the heatspreader.
  11. Bish, Jack; Brink, Damon; Hanrahan, Kevin, Integrated heat spreader lid.
  12. Hoang Lan H., Leaded substrate carrier for integrated circuit device and leaded substrate carrier device assembly.
  13. Anderson,Russell J., Making integral heat spreader by coining.
  14. Shaw Wei Lee ; Hem P. Takiar, Manufacturing methods and construction for integrated circuit packages.
  15. Edwards David L. ; Emmett Michael J. ; Iruvanti Sushumna ; Sherif Raed A. ; Sikka Kamal ; Toy Hilton T., Method for controlling thermal interface gap distance.
  16. Chan Joseph Ying-Yuen ; Pavelka John B. ; Pompeo Frank L. ; Toy Hilton T., Microelectronic package module with temporary lid.
  17. Chan Joseph Ying-Yuen ; Pavelka John B. ; Pompeo Frank L. ; Toy Hilton T., Process for adhesively attaching a temporary lid to a microelectronic package.
  18. Terui Makoto,JPX, Semiconductor device.
  19. Terui, Makoto, Semiconductor device.
  20. Takahashi, Satoshi; Kariyazaki, Shuuichi, Semiconductor device with covering member that partially covers wiring substrate.
  21. Luo, Shijian; Li, Xiao; Li, Jian, Semiconductor die assemblies with enhanced thermal management and semiconductor devices including same.
  22. Park, Young-woo, Semiconductor package.
  23. Tang Tom,TWX ; Huang Chien Ping,TWX ; Chiang Kevin,TWX ; Lai Jeng-Yuan,TWX ; Tien Candy,TWX ; Liu Vicky,TWX, Semiconductor package having a heat sink with an exposed surface.
  24. Groothuis, Steven K.; Li, Jian; Zhang, Haojun; Silvestri, Paul A.; Li, Xiao; Luo, Shijian; England, Luke G.; Keeth, Brent; Gandhi, Jaspreet, Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods.
  25. Groothuis, Steven K.; Li, Jian; Zhang, Haojun; Silvestri, Paul A.; Li, Xiao; Luo, Shijian; England, Luke G.; Keeth, Brent; Gandhi, Jaspreet S., Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods.
  26. Yuan,Tsorng Dih; Pan,Hsin Yu; Lin,Chung Yi, Structural design for flip-chip assembly.
  27. Atwood Eugene R. ; Benenati Joseph A. ; DiGiacomo Giulio ; Quinones Horatio, Thermal enhancement approach using solder compositions in the liquid state.
  28. Atwood, Eugene R.; Benenati, Joseph A.; DiGiacomo, Giulio; Quinones, Horatio, Thermal enhancement approach using solder compositions in the liquid state.
  29. Distefano Thomas H., Thermally enhanced packaged semiconductor assemblies.
  30. Thomas H. Distefano, Thermally enhanced packaged semiconductor assemblies.
  31. Chen, Wei-Yu; Hu, Yu-Hsiang (James); Lin, Wei-Hung; Cheng, Ming-Da; Liu, Chung-Shi, Warpage control in package-on-package structures.
  32. Chen, Wei-Yu; Hu, Yu-Hsiang; Lin, Wei-Hung; Cheng, Ming-Da; Liu, Chung-Shi, Warpage control in package-on-package structures.
  33. Chen, Wei-Yu; Hu, Yu-Hsiang; Lin, Wei-Hung; Cheng, Ming-Da; Liu, Chung-Shi, Warpage control in package-on-package structures.
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