초록 ▼

A clock signal generator or frequency multiplier generates an output signal having a frequency which is a non-integer multiple of an input signal frequency. One clock signal generator contains one or more shift registers. A signal generated from a logical combination of bits from the shift registers

A clock signal generator or frequency multiplier generates an output signal having a frequency which is a non-integer multiple of an input signal frequency. One clock signal generator contains one or more shift registers. A signal generated from a logical combination of bits from the shift registers transitions from high to low or low to high as values in the shift registers shift. The transitions have a pattern which repeats each time values in the shift registers return to their initial states and the initial states stored in the shift registers control the number of transitions per repetition. The frequency of the combined signal is the frequency of the input signal times the ratio of the number of transitions per repetition to the number of shifts per repetition. One embodiment of the invention provides a 1.33x multiple of an input clock signal. Using a 1.33x multiple of a nominally highest frequency input clock signal from a set of input clock signals provides an output clock signal having a frequency greater than any input clock signal in the set even if the frequencies of the input clock signals vary from their nominal frequencies by up to 10%.

대표청구항 ▼

[ We claim:] [1.] A clock generator, comprising:a first shift register that generates a first signal representing a bit from a first value stored in the first shift register, wherein the first value includes multiple bits and in response to a first trigger signal that is a positive edge of an input

[ We claim:] [1.] A clock generator, comprising:a first shift register that generates a first signal representing a bit from a first value stored in the first shift register, wherein the first value includes multiple bits and in response to a first trigger signal that is a positive edge of an input clock signal, the first shift register changes which bit of the first value the first signal represents;a second shift register that generates a second signal representing a bit from a second value stored in the second shift register, wherein the second value includes multiple bits and in response to a second trigger signal that is a negative edge of the input clock signal, the second shift register changes which bit of the second value the second signal represents; andcombination logic coupled to the first and second shift registers, wherein the combination logic generates an output clock signal that is a logical combination of the first and second signals.