초록 ▼

A configurable multiprocessor communications architecture which performs digital communications functions and which is configurable for different digital communications standards, such as various digital cellular standards. In the preferred embodiment, the multiprocessor architecture includes two or

A configurable multiprocessor communications architecture which performs digital communications functions and which is configurable for different digital communications standards, such as various digital cellular standards. In the preferred embodiment, the multiprocessor architecture includes two or more digital signal processing cores, a microcontroller or micro-scheduler, a voice coder/decoder (codec), and a relatively low performance central processing unit (CPU). Each of the above devices are coupled to a system memory. The general purpose CPU preferably performs user interface functions and overall communications management functions. A CPU local memory and various peripheral devices are coupled through a CPU local bus to the CPU, and these devices are accessible to the CPU without the CPU having to access the main system bus. A dual port bus arbiter is preferably coupled between the CPU and the system bus and controls access to the system bus and the CPU local bus. The micro-scheduler operates to schedule operations and/or functions, as well as dynamically control the clock rates, of each of the DSPs and the hardware acceleration logic to achieve the desired throughput while minimizing power consumption. The present invention thus provides a single architecture which has simplified configurability for different digital standards. The configurable digital communications architecture simplifies design and manufacturing costs and provides improved performance over prior designs.

대표청구항 ▼

[ We claim:] [1.] A digital wireless communication system for performing communications according to one of a plurality of different digital standards, wherein the system is configurable to operate according to different ones of said plurality of digital standards, the digital wireless communication

[ We claim:] [1.] A digital wireless communication system for performing communications according to one of a plurality of different digital standards, wherein the system is configurable to operate according to different ones of said plurality of digital standards, the digital wireless communication system comprising, on a single integrated circuit:a system bus for transmitting data;system memory coupled to the system bus for storing code and data;one or more digital signal processors (DSPs) coupled to the system bus for performing communication functions;a microcontroller coupled to said system bus which controls operations of said one or more digital signal processors, wherein the microcontroller is configured to access code and data from the system memory, wherein the microcontroller is configured to control operations of the one or more digital signal processors;a voice coder/decoder (codec) coupled to the system bus, wherein the voice codec includes analog to digital conversion logic and digital to analog conversion logic;a central processing unit (CPU) coupled to the system bus, wherein the CPU implements one of a plurality of possible protocol stacks for digital communication;a bus arbiter coupled to the system bus which controls arbitration and access to the system bus, wherein the bus arbiter is configured to receive requests from each of the microcontroller and the CPU for access to the system bus and selectively grant control of the system bus to one of either the microcontroller or the CPU;a CPU local memory coupled to the CPU, wherein the CPU local memory stores code and data used by the CPU for performing communication control operations;wherein the CPU is operable to write code and data to the system memory to configure the microcontroller to perform desired functions; andwherein the microcontroller is configured to read said code and data written by the CPU and selectively assign functions to the one or more digital signal processors based on said code and data written by the CPU.