초록 ▼

A process for metallizing an integrated circuit chip to form an interconnecting pattern for the chip's input/output terminals, wherein the process can be performed while the chip is still a part of the wafer on which it is fabricated and before separation into individual chips. The invention uses ph

A process for metallizing an integrated circuit chip to form an interconnecting pattern for the chip's input/output terminals, wherein the process can be performed while the chip is still a part of the wafer on which it is fabricated and before separation into individual chips. The invention uses photodefinable resins as masks that form permanent dielectric layers of a multilayer structure with which interconnecting paths and terminals are defined on the surface of the chip. The process further employs conversion techniques that enable the interconnecting paths to be formed from metals other than aluminum, such that the electrical performance of the chip is enhanced. The use of the photodefinable resins renders the process of this invention conducive to inline processing techniques, thereby reducing processing costs while promoting high throughput and short cycle times. The process of this invention also enables the interconnecting paths to be readily customized for adaption to changing configuration requirements at the next assembly level, while also promoting greater dimensional precision of bumps formed at the terminals.

대표청구항 ▼

[ The embodiments of this invention in which an exclusive property or privilege is claimed are defined as follows:] [1.] A method for metallizing an integrated circuit chip having aluminum metallization exposed at a surface thereof, the method comprising the steps of:depositing a first photodefinabl

[ The embodiments of this invention in which an exclusive property or privilege is claimed are defined as follows:] [1.] A method for metallizing an integrated circuit chip having aluminum metallization exposed at a surface thereof, the method comprising the steps of:depositing a first photodefinable resin containing a catalytic filler on the surface of the integrated circuit chip and over the aluminum metallization so as to form a first dielectric layer;photoimaging and developing the first dielectric layer so as to expose at least a portion of the aluminum metallization;depositing a second photodefinable resin on the first dielectric layer and over the portion of the aluminum metallization so as to form a second dielectric layer;photoimaging and developing the second dielectric layer so as to re-expose the portion of the aluminum metallization and to expose a surface portion of the first dielectric layer contiguous with the portion of the aluminum metallization;depositing a catalytic metal on the portion of the aluminum metallization so as to form a catalytic metal layer thereon, the catalytic metal being less active than aluminum;treating the surface portion of the first dielectric layer such that the catalytic filler causes the surface portion to be plateable; andelectrolessly plating a conductive material on the surface portion of the first dielectric layer and the metal layer so as to form a conductor that is electrically interconnected with the aluminum metallization through the metal layer.