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Structure for controlling threshold voltage of MOSFET 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/76
  • H01L-029/94
  • H01L-031/062
  • H01L-031/113
출원번호 US-0664440 (1996-06-18)
발명자 / 주소
  • Choi Jeong Yeol
  • Chien Chung-Jen
  • Han Chung Chyung
  • Lien Chuen-Der
출원인 / 주소
  • Integrated Device Technology, Inc.
대리인 / 주소
    Skjerven,Morrill, MacPherson,Franklin & Friel
인용정보 피인용 횟수 : 67  인용 특허 : 7

초록

A method and structure for controlling the threshold voltage of a MOSFET is provided. The method compensates for the edge effect associated with prior art halo implants by providing an edge threshold voltage implant (the VT implant) which passes impurities through dielectric spacers, through the und

대표청구항

[ We claim:] [1.] A semiconductor device having a substrate with a gate structure formed over said substrate, said gate structure having a first side connected to a first spacer, said semiconductor device comprising:a first source/drain region and a channel region in said substrate, said channel reg

이 특허에 인용된 특허 (7)

  1. Arimura Motoharu (Tenri JPX) Adan Alberto O. (Tenri JPX), Field effect transistor with short channel and manufacturing method therefor.
  2. Kaneshiro Michael H. (Phoenix AZ) Dow Diann (Chandler AZ), Insulated gate field effect transistor and method for fabricating.
  3. Ravindhran K. S. (San Antonio TX) Han Yu P. (Dallas TX) Jhota Ravi (San Antonio TX) Parmantie Walter D. (San Antonio TX), MOSFET with gate-penetrating halo implant.
  4. Burr James B. (Foster City CA) Brassington Michael P. (Sunnyvale CA), Method of making asymmetric low power MOS devices.
  5. Sakagami Eiji (Kawasaki JPX), Method of manufacturing semiconductor device by controlling the profile of the density of p-type impurities in the sourc.
  6. Ahmad Aftab (Boise ID) Lowrey Tyler A. (Boise ID), Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers.
  7. Kaneko Seiji (Joyo JPX) Baba Tomoya (Nara JPX), Semiconductor device with LDD structure.

이 특허를 인용한 특허 (67)

  1. Rhodes,Howard E., Asymmetrical transistor for imager device.
  2. Radosavljevic,Marko; Majumdar,Amlan; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark L.; Brask,Justin K.; Shah,Uday; Datta,Suman; Chau,Robert S., Block contact architectures for nanoscale channel transistors.
  3. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  4. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  5. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  6. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  7. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  8. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  9. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  10. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  11. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  14. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  15. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  16. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  17. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  18. Rodder Mark S., Lateral MOSFET having a barrier between the source/drain regions and the channel.
  19. Gambino, Jeffrey P.; Mandelman, Jack; Tonti, William R., Low-K gate spacers by fluorine implantation.
  20. Gambino,Jeffrey P.; Mandelman,Jack; Tonti,William R., Low-K gate spacers by fluorine implantation.
  21. Murthy,Anand; Chau,Robert S.; Morrow,Patrick, MOS transistor structure and method of fabrication.
  22. Akira Hiroki JP; Shinji Odanaka JP, MOS type semiconductor device having an impurity diffusion layer.
  23. Hiroki Akira,JPX ; Odanaka Shinji,JPX, MOS type semiconductor device having an impurity diffusion layer with a nonuniform impurity concentration profile in a channel region.
  24. Noda, Taiji, Method for fabricating semiconductor device.
  25. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  26. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  27. Ahn, Jae-Gyung, Method for forming localized halo implant regions.
  28. Sohn, Young-Sun; Jin, Seung-Woo; Lee, Min-Yong; Rouh, Kyoung-Bong, Method for implanting ions in semiconductor device.
  29. Holloway Thomas C., Method to reduce diode capacitance of short-channel MOSFETS.
  30. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  31. Zhang,Yuegang; Doyle,Brian S.; Bourianoff,George I., Multi-gate carbon nano-tube transistors.
  32. Lai, Li-Shyue; Chen, Hung-Wei; Lee, Wen-Chin; Chi, Min-Hwa, Multi-level flash memory cell capable of fast programming.
  33. Doyle,Brian S; Datta,Suman; Jin,Been Yih; Zelick,Nancy M; Chau,Robert, Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow.
  34. Lee, Yong-Kyu, Non-volatile semiconductor device with anti-punch through regions.
  35. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  36. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  37. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  41. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
  42. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
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  45. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
  46. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
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  48. Hodges,Robert Louis, Self-aligned gate and method.
  49. Shima, Masashi, Semiconductor device and method for manufacturing semiconductor device.
  50. Shima, Masashi, Semiconductor device having channel dose region and method for manufacturing semiconductor device.
  51. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
  52. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
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  55. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
  56. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  57. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
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  60. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
  61. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman, Tri-gate devices and methods of fabrication.
  62. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman; Hareland, Scott A., Tri-gate devices and methods of fabrication.
  63. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman, Tri-gate devices and methods of fabrication.
  64. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman, Tri-gate devices and methods of fabrication.
  65. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman; Hareland,Scott A., Tri-gate devices and methods of fabrication.
  66. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
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