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Microelectronic packaging using arched solder columns 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-029/40
출원번호 US-0654539 (1996-05-29)
발명자 / 주소
  • Rinne Glenn A.
  • Deane Philip A.
출원인 / 주소
  • MCNC
대리인 / 주소
    Alston & Bird
인용정보 피인용 횟수 : 42  인용 특허 : 22

초록 ▼

Microelectronic packages are formed wherein solder bumps on one or more substrates are expanded, to thereby extend and contact the second substrate and form a solder connection. The solder bumps are preferably expanded by reflowing additional solder into the plurality of solder bumps. The additional

대표청구항 ▼

[ That which is claimed:] [1.] A microelectronic package comprising:a first microelectronics substrate;a second microelectronic substrate which is oriented relative to said first microelectronic substrate. such that an edge of said second microelectronic substrate is adjacent said first microelectro

이 특허에 인용된 특허 (22)

  1. Amano Toshiaki (Hiratsuka JPX) Hikasa Kazuhito (Hiratsuka JPX) Kumamoto Seishi (Kakogawa JPX) Fujiwara Takahiro (Ono JPX), Circuit board to be precoated with solder layers and solder circuit board.
    상세보기
  2. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
    상세보기
  3. Carson John C. (Corona del Mar CA) Some Raphael R. (Irvine CA), Electronic module comprising a stack of IC chips each interacting with an IC chip secured to the stack.
    상세보기
  4. Pepe Angel A. (Irvine CA) Reinker David M. (Rancho Santa Margarita CA) Minahan Joseph A. (Simi Valley CA), Fabrication of dense parallel solder bump connections.
    상세보기
  5. Wheeler Richard L. (San Jose CA) Nagesh Voddarahalli K. (Cupertino CA), High-speed, high-density chip mounting.
    상세보기
  6. Kondo Kenji (Hoi JPX) Kunda Hachiro (Chiryu JPX) Sonobe Toshio (Okazaki JPX), Method for making a semiconductor device.
    상세보기
  7. Dishon Giora J. (Chapel Hill NC), Method of building solder bumps.
    상세보기
  8. Del Monte ; Louis A., Microcircuit device metallization.
    상세보기
  9. Carson John C. (Corona del Mar CA) Indin Ronald J. (Huntington Beach CA) Shanken Stuart N. (Irvine CA), Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip.
    상세보기
  10. Eichelberger Charles W. (Schenectady NY), Multichip integrated circuit modules.
    상세보기
  11. Miyake Michael K. (Westminster CA), Non-conductive end layer for integrated stack of IC chips.
    상세보기
  12. Malhi Satwinder (Garland TX) Bean Kenneth E. (Celina TX) Driscoll Charles C. (Richardson TX) Chatterjee Pallab K. (Dallas TX), Orthogonal chip mount system module and method.
    상세보기
  13. Heitzmann Michel (Crolles FRX) Lajzerowicz Jean (Meylan FRX) LaPorte Philippe (Sassenage FRX), Process for etching and depositing integrated circuit interconnections and contacts.
    상세보기
  14. Cronin John E. (Milton VT) Lee Pei-ing P. (Williston VT), Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit.
    상세보기
  15. Gelsing Richardus Johannes Henricus (Eindhoven NL) VAN Steensel Kees (Eindhoven NL), Semiconductor device with multi-layered metal interconnections.
    상세보기
  16. Ishikawa Toshimitsu (Kawaguchi JPX) Kitamura Atsushi (Tokyo JPX) Hirayama Kenji (Ooita JPX), Semiconductor integrated circuit devices having particular terminal geometry.
    상세보기
  17. Yung Edward K. (Carrboro NC), Solder bump fabrication method.
    상세보기
  18. Yung Edward K. (Carrboro NC), Solder bump including circular lip.
    상세보기
  19. Moore Kevin D. (Schaumburg IL) Missele Carl (Elgin IL), Solder bumping of integrated circuit die.
    상세보기
  20. Moore Kevin D. (Schaumburg IL) Stafford John W. (St. Charles IL) Beckenbaugh William M. (Barrington IL) Cholewczynski Ken (Streamwood IL), Solder plate reflow method for forming a solder bump on a circuit trace intersection.
    상세보기
  21. Moore Kevin D. (Schaumburg) Stafford John W. (St. Charles) Beckenbaugh William M. (Barrington) Cholewczynski Ken (Streamwood IL), Solder plate reflow method for forming solder-bumped terminals.
    상세보기
  22. Frew Dean L. (Garland TX) Kressley Mark A. (Richardson TX) Wilson Arthur M. (Richardson TX) Miller Juanita G. (Richardson TX) Hecker ; Jr. Philip E. (Garland TX) Drumm James (Crystal Lake IL) Johnson, Three dimensional assembly of integrated circuit chips.
    상세보기

이 특허를 인용한 특허 (42)

  1. Baleras, François; Souriau, Jean-Charles; Poupon, Gilles; Verrun, Sophie, 3D integration of vertical components in reconstituted substrates.
    상세보기
  2. Farrar, Paul A., Angled edge connections for multichip structures.
    상세보기
  3. Kinsman,Larry D., Back-to-back semiconductor device assemblies.
    상세보기
  4. Larry D. Kinsman, Back-to-back semiconductor device module, assemblies including the same and methods.
    상세보기
  5. Hu, Chih-Liang; Chen, Wen-Long; Chen, Pan-Nan; Liang, Ming-Chong; Yu, Cheen-Hai, Discrete circuit component having an up-right circuit die with lateral electrical connections.
    상세보기
  6. Jan, Jong Rong; Lu, Tsai Hua; Chiu, Sao Ling; Kung, Ling Chen, Electronic devices including offset conductive bumps.
    상세보기
  7. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive shunt layers.
    상세보기
  8. Grigg, Ford B., Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods.
    상세보기
  9. Rinne,Glenn A.; Nair,Krishna K., Low temperature methods of bonding components and related structures.
    상세보기
  10. Grigg,Ford B., Method for fabricating interposers including upwardly protruding dams, semiconductor device assemblies including the interposers.
    상세보기
  11. Grigg,Ford B., Methods for fabricating interposers including upwardly protruding dams.
    상세보기
  12. Kinsman,Larry D., Methods for securing vertically mountable semiconductor devices in back-to back relation.
    상세보기
  13. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Methods of forming electronic structures including conductive shunt layers and related structures.
    상세보기
  14. Nair,Krishna K.; Rinne,Glenn A.; Batchelor,William E., Methods of forming electronic structures including conductive shunt layers and related structures.
    상세보기
  15. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Methods of forming lead free solder bumps.
    상세보기
  16. Rinne, Glenn A., Methods of forming metal layers using multi-layer lift-off patterns.
    상세보기
  17. Mis,J. Daniel, Methods of forming solder bumps on exposed metal pads.
    상세보기
  18. Rinne,Glenn A., Methods of providing solder structures for out plane connections.
    상세보기
  19. Jan,Jong Rong; Lu,Tsai Hua; Chiu,Sao Ling; Kung,Ling Chen, Methods of selectively bumping integrated circuit substrates and related structures.
    상세보기
  20. Glenn A. Rinne, Microelectronic packages in which second microelectronic substrates are oriented relative to first microelectronic substrates at acute angles.
    상세보기
  21. Rinne Glenn A., Microelectronic radiation detectors for detecting and emitting radiation signals.
    상세보기
  22. Morkner,Henrik, Multi-mode integrated circuit structure.
    상세보기
  23. Morkner,Henrik, Multi-mode integrated circuit structure.
    상세보기
  24. Batchelor, William E.; Rinne, Glenn A., Non-Circular via holes for bumping pads and related structures.
    상세보기
  25. Rinne,Glenn A., Optical structures including liquid bumps and related methods.
    상세보기
  26. DCamp,Jon B.; Curtis,Harlan L., Package for MEMS devices.
    상세보기
  27. Oppermann,Hans Hermann; Zakel,Elke; Azdasht,Ghassem; Kasulke,Paul, Process for the formation of a spatial chip arrangement and spatial chip arrangement.
    상세보기
  28. Hall, Douglas C.; Howard, Scott; Hoffman, Anthony; Bernstein, Gary H.; Kulick, Jason M., Quilt packaging system with interdigitated interconnecting nodules for inter-chip alignment.
    상세보기
  29. Azdasht, Ghassem, Semiconductor chip assembly and method for manufacturing the same.
    상세보기
  30. Grigg, Ford B., Semiconductor device assemblies including interposers with dams protruding therefrom.
    상세보기
  31. Grigg,Ford B., Semiconductor device assemblies including interposers with dams protruding therefrom.
    상세보기
  32. Kinsman Larry ; Akram Salman, Semiconductor device comprising a socket and method for forming same.
    상세보기
  33. Kinsman, Larry; Akram, Salman, Semiconductor device comprising a socket and method for forming same.
    상세보기
  34. Nam, Tae-Duk; Kim, Jin-Ho; Kim, Hyuk-Su; Kim, Hyoung-Suk; Lee, Tae-Young, Semiconductor package having supporting plate and method of forming the same.
    상세보기
  35. Nam, Tae-Duk; Kim, Jin-Ho; Kim, Hyuk-Su; Kim, Hyoung-Suk; Lee, Tae-Young, Semiconductor package having supporting plate and method of forming the same.
    상세보기
  36. Rinne, Glenn A., Solder structures for out of plane connections.
    상세보기
  37. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Solder structures including barrier layers with nickel and/or copper.
    상세보기
  38. Rinne,Glenn A., Stacked electronic structures including offset substrates.
    상세보기
  39. Kinsman Larry D., Vertical surface mount package utilizing a back-to-back semiconductor device module.
    상세보기
  40. Kinsman, Larry D., Vertical surface mount package utilizing a back-to-back semiconductor device module.
    상세보기
  41. Kinsman, Larry D., Vertical surface mount package utilizing a back-to-back semiconductor device module.
    상세보기
  42. Larry D. Kinsman, Vertical surface mount package utilizing a back-to-back semiconductor device module.
    상세보기

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