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Cell placement alteration apparatus for integrated circuit chip physical design automation system 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/50
출원번호 US-0724025 (1996-09-17)
발명자 / 주소
  • Koford James S.
  • Scepanovic Ranko
  • Jones Edwin R.
  • Boyle Douglas B.
  • Rostoker Michael D.
출원인 / 주소
  • LSI Logic Corporation
대리인 / 주소
    Oppenheimer Wolff & Donnelly LLP
인용정보 피인용 횟수 : 25  인용 특허 : 35

초록

A large number of possible placements of cells on an integrated circuit chip are generated and evaluated to determine the placement with the highest fitness. Cells for transposition or "swapping" within each placement using genetic algorithms are selected using greedy algorithms based on the fitness

대표청구항

[ We claim:] [1.] A method for selecting cells for transposition such that a probability of each cell being selected is a predetermined function of a fitness associated with each cell respectively, comprising the steps of:sorting and ranking said cells in increasing order of fitness;multiplying said

이 특허에 인용된 특허 (35)

  1. Davis Lawrence (Cambridge MA), Adaptive computing system.
  2. Holland John H. (3800 W. Huron River Dr. Ann Arbor MI 48103) Burks Arthur W. (3445 Vintage Valley Rd. Ann Arbor MI 48105), Adaptive computing system capable of learning and discovery.
  3. Rogers Donald L. (San Jose CA), Apparatus and method for tracking and identifying printed circuit assemblies.
  4. Miki Yoshio (Kokubunji JPX) Suzuki Kei (Kokubunji CA JPX) Takamine Yoshio (Albany CA), Apparatus for wire routing of VLSI.
  5. Hooper Donald F. (Northboro MA) Kundu Snehamay (Marlboro MA), Bitwise implementation mechanism for a circuit design synthesis procedure.
  6. Koford James S. (San Jose CA) Scepanovic Ranko (Cupertino CA) Jones Edwin R. (Sunnyvale CA) Boyle Douglas B. (Palo Alto CA) Rostoker Michael D. (Boulder Creek CA), Cell placement alteration apparatus for integrated circuit chip physical design automation system.
  7. Kimmel Milton J. (Somers NY), Configurable parallel pipeline image processing system.
  8. Davis James W. (Boca Raton FL), Differential cascode current switch (DCCS) master slice for high efficiency/custom density physical design.
  9. Handa Keiichi (Kawasaki JPX), Element placement method and apparatus.
  10. Shaefer Craig G. (Charlestown MA), Genetic algorithm.
  11. Guha Aloke (Minneapolis MN) Harp Steven A. (St. Paul MN) Samad Tariq (Minneapolis MN), Genetic algorithm synthesis of neural networks.
  12. Harvey Robert L. (Lexington MA), Genetic algorithm technique for designing neural networks.
  13. Pryor Richard L. (Voorhees NJ) Cowhig William M. (Philadelphia PA), Hierarchical, computerized design of integrated circuits.
  14. Hong Se J. (Yorktown Heights NY) Nair Ravindra K. (Peekskill NY) Shapiro Eugene (Stamford CT), High speed machine for the physical design of very large scale integrated circuits.
  15. Chi Mely C. (Murray Hill NJ), Integrated circuits with component placement by rectilinear partitioning.
  16. Linsker Ralph (Scarsdale NY), Iterative method for establishing connections and resulting product.
  17. Kaida Hiromasa (Chiba JPX), Logic cell placement method for semiconductor integrated circuit.
  18. Chene Mon R. (Cupertino CA) Trimberger Stephen M. (San Jose CA), Logic placement using positionally asymmetrical partitioning algorithm.
  19. Cocke John (Bedford Village NY) Malm Richard L. (San Jose CA) Shedletsky John J. (North Salem NY), Logic simulation machine.
  20. Hitchcock ; Sr. Robert B. (Binghamton NY) Graf Matthew C. (Highland NY), Logic simulation machine.
  21. Bischoff Gabriel P. (Marlboro MA) Greenberg Steven S. (Bolton MA), Method and apparatus for circuit simulation using parallel processors including memory arrangements and matrix decomposi.
  22. Date Hiroshi (Hitachi JPX) Hayashi Terumine (Hitachi JPX), Method and apparatus for optimizing element placement and method and apparatus for deciding the optimal element placemen.
  23. Wong Dale M. (San Francisco CA), Method for partitioning of connected circuit components before placement in one or more integrated circuits.
  24. Wong Dale M. (San Francisco CA), Method for placement of circuit components in an integrated circuit.
  25. Antreich Kurt (Germering DEX) Johannes Frank (Germering DEX) Kleinhans Jurgen (Munich DEX) Sigl Georg (Tutzing DEX), Method for placing modules on a carrier.
  26. Finnerty James L. (Lexington MA), Minimizing the interconnection cost of electronically linked objects.
  27. Catlin Gary M. (Cupertino CA), Multiple processor accelerator for logic simulation.
  28. Koza John R. (25372 La Rena La. Los Altos Hills CA 94022), Non-linear genetic algorithms for solving problems by finding a fit composition of functions.
  29. Gelatt ; Jr. Charles D. (Chappaqua NY) Kirkpatrick Edward S. (Croton-on-Hudson NY), Optimization of an organization of many discrete elements.
  30. McDermith William O. (Colorado Springs CO) Banki Mehrdad (Colorado Springs CO) Bush Kevin M. (Colorado Springs CO), Partitioning of Boolean logic equations into physical logic devices.
  31. Okude Hiroaki (Takatsuki JPX) Toyonaga Masahiko (Takatsuki JPX) Akino Toshiro (Takatsuki JPX), Placement optimization system aided by CAD.
  32. Date Hiroshi (Hitachi) Hayashi Terumine (Hitachi JPX), Placement optimizing method/apparatus and apparatus for designing semiconductor devices.
  33. Wagner Robert A. (Durham NC) Poirier Charles J. (Red Bank NJ), SIMD machine using cube connected cycles network architecture for vector processing.
  34. Toyonaga Masahiko (Osaka JPX) Akino Toshiro (Osaka JPX) Okude Hiroaki (Osaka JPX), System for optimizing a physical organization of elements of an integrated circuit chip through the convergence of a red.
  35. Agrawal Bhuwan (Chapel Hill NC) Bello Stephen E. (Kingston NY) Donath Wilm E. (Pleasantville NY) Han San Y. (Poughkeepsie NY) Hutt ; Jr. Joseph (Poughkeepsie NY) Kurtzberg Jerome M. (Yorktown Heights, Timing driven placement.

이 특허를 인용한 특허 (25)

  1. Hoffberg, Steven, Agent training sensitive call routing system.
  2. Hoffberg, Steven M., Agent training sensitive call routing system.
  3. Peters, Jason; Padalia, Ketan; Ludwin, Adrian, Apparatus and methods for congestion estimation and optimization for computer-aided design software.
  4. Kikuchi Yasuhiro,JPX ; Doi Hirofumi,JPX, Device, method, and program storage medium for executing genetic algorithm.
  5. Griffin, Jed D., Differential amplifier output stage.
  6. Baskent, Deniz; Durant, Eric, Genetic algorithms with robust rank estimation for hearing assistance devices.
  7. Durant, Eric A., Hearing aids and methods and apparatus for audio fitting thereof.
  8. Durant, Eric A., Hearing aids and methods and apparatus for audio fitting thereof.
  9. Kim, Myung-Chul; Ramji, Shyam; Villarrubia, Paul G.; Viswanathan, Natarajan, Large cluster persistence during placement optimization of integrated circuit designs.
  10. Kim, Myung-Chul; Ramji, Shyam; Villarrubia, Paul G.; Viswanathan, Natarajan, Large cluster persistence during placement optimization of integrated circuit designs.
  11. Self, Keith; Urbanski, John, Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect.
  12. Khare, Manoj; Kumar, Akhilesh; Creta, Ken; Looi, Lily P.; George, Robert T.; Cekleov, Michel, Method and apparatus for invalidating a cache line without data return in a multi-node architecture.
  13. Khare, Manoj; Kumar, Akhilesh; Schoinas, Ioannis; Looi, Lily Pao, Method and apparatus for managing transaction requests in a multi-node architecture.
  14. Khare, Manoj; Kumar, Akhilesh; Tan, Sin Sim, Method and apparatus for preventing starvation in a multi-node architecture.
  15. Manoj Khare ; Akhilesh Kumar, Method and apparatus for preventing starvation in a multi-node architecture.
  16. Khare,Manoj; Briggs,Faye A.; Kumar,Akhilesh; Looi,Lily P.; Cheng,Kai, Method and apparatus for reducing memory latency in a cache coherent multi-node architecture.
  17. Saito, Muneto; Suzuki, Koichi; Sakurai, Mitsuo; Nagase, Norimasa, Method of making pattern data, and medium for storing the program for making the pattern data.
  18. Hsu, Chin-Hsiung; Yang, Chun-Chih, Methods for reducing congestion region in layout area of IC.
  19. Stenz,Guenter, Methods of structured placement of a circuit design.
  20. Pucci, Steven Lee; Nequist, Eric Martin, Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit.
  21. Alpert, Charles Jay; Nam, Gi-Joon; Roy, Jarrod Alexander; Vishvanathan, Natarajan, Object placement in integrated circuit design.
  22. Masayuki Hayashi ; Richard F. Keil ; Robert J. Savaglio, On-demand process sorting method and apparatus.
  23. Yamasaki, Kazuhito, Semiconductor design system, semiconductor integrated circuit, semiconductor design method and storage medium storing semiconductor design program.
  24. Wang, Shen; Utsumi, Tetsuaki; Sekine, Mizue, Semiconductor layout design apparatus and method for evaluating a floorplan using distances between standard cells and macrocells.
  25. Woods, William S.; Edwards, Brent, System for customizing hearing assistance devices.
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