초록 ▼

A processor clock (302) is momentarily synchronized to a subsystem clock (307) during transfers of data between a processor (301) and a subsystem (305). After the completion of the data transfer, synchronization is disabled and the processor clock runs asynchronously at its own internal frequency, w

A processor clock (302) is momentarily synchronized to a subsystem clock (307) during transfers of data between a processor (301) and a subsystem (305). After the completion of the data transfer, synchronization is disabled and the processor clock runs asynchronously at its own internal frequency, which is higher than the subsystem clock frequency. In one embodiment, the processor clock uses a free running ring oscillator (401) that is constructed on the same integrated circuit chip as the processor. Changes in temperature and power supply voltage not only cause changes in the maximum operating speed of the processor, but they also cause corresponding changes in the frequency of the processor clock. Thus, the frequency of the processor clock tracks changes in the maximum operating speed of the processor caused by temperature and power supply variations.

대표청구항 ▼

[ We claim as our invention:] [1.] A computer system, comprising:an integrated circuit chip including a processor and a processor clock, said processor including a plurality of gates, said processor clock including a free running, variable frequency oscillator wherein, in an asynchronous mode, the f

[ We claim as our invention:] [1.] A computer system, comprising:an integrated circuit chip including a processor and a processor clock, said processor including a plurality of gates, said processor clock including a free running, variable frequency oscillator wherein, in an asynchronous mode, the frequency of said processor clock is determined in part by the temperature of said chip and the voltage applied to said chip such that, as the propagation delay of said gates decreases with changes in the temperature and the voltage, the frequency of said processor clock increases, and as the propagation delay of said gates increases with changes in the temperature and the voltage, the frequency of said processor clock decreases;a computer subsystem having a subsystem clock, said computer subsystem being coupled to said processor such that data can be transferred between said processor and said subsystem;signaling means for generating a synchronizing signal that precedes a transfer of a block of data between said processor and said subsystem;synchronizing means for providing momentary synchronization of said processor clock and said subsystem clock, said momentary synchronization being initialized by said synchronizing signal and terminating upon the completion of the transfer of a block of data;whereby said processor clock operates in a selected one of the asynchronous mode in which said processor clock and said subsystem clock are unsynchronized, and a synchronous mode in which said processor clock is synchronized to said subsystem clock, said synchronous mode being selected during the transfer of a block of data.