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Integrated circuit chip to substrate interconnection and method 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-7614721 (1996-12-06)
발명자 / 주소
  • Marrs Robert C.
출원인 / 주소
  • Amkor Technology, Inc.
대리인 / 주소
    Skjerven, Morill, MacPherson, Franklin & Friel LLPMacDonald
인용정보 피인용 횟수 : 66  인용 특허 : 30

초록 ▼

An interconnection between bonding pads on an integrated circuit chip and corresponding bonding contacts on a substrate are formed. To form the interconnection, a metallization is formed on each of the substrate bonding contacts. Metal ball bond bumps are formed on selective ones of the bonding pads

대표청구항

[ I claim:] [1.] A method for forming an interconnection between an integrated circuit chip and a substrate, said method comprising the steps of:

이 특허에 인용된 특허 (30)

  1. Pasch Nicholas F. (Redwood City CA) Sahakian Vahak K. (Los Altos Hills CA) Dell\Oca Conrad J. (Palo Alto CA), Apparatus for isolation of flux materials in “flip-chip”manufacturing.
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  2. Wang Tsing-Chow (San Jose CA) Luo Serena M. (Milpitas CA) Macaraeg Marlita F. (Milpitas CA) Tung Francisca (Los Gatos CA) Massingill Thomas J. (Scotts Valley CA), Bump formation on yielded semiconductor dies.
    상세보기
  3. Lam Ken (Colorado Springs CO), Bumpless bonding process having multilayer metallization.
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  4. Missele Carl (Elgin IL), Compliant solder interconnection.
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  5. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
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  6. Berner Gianni (Baden CHX), Electronic circuit and method of production thereof.
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  7. Carey David H. (Austin TX), Flip substrate for chip mount.
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  8. Gnadinger Alfred P. (Colorado Springs CO), High density data storage using stacked wafers.
    상세보기
  9. Marrs Robert C. (Scottsdale AZ) Hirakawa Tadashi (Osaka JPX), Integrated circuit package with via interconnections formed in a substrate.
    상세보기
  10. Gansauge Peter (Boeblingen DEX) Kreuter Volker (Schoenaich DEX) Schettler Helmut (Dettenhausen DEX), Integrated circuit substrate with contacts thereon for a packaging structure.
    상세보기
  11. Behun John R. (Poughkeepsie NY) Call Anson J. (Poughkeepsie NY) Cappo Francis F. (Wappingers Falls NY) Cole Marie S. (Wappingers Falls NY) Hoebener Karl G. (Georgetown TX) Klingel Bruno T. (Hopewell , Interconnection structure and test method.
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  12. Ozawa Kazuhito (Nara JPX), LSI chip and method of producing same.
    상세보기
  13. Tago Masamoto (Tokyo JPX) Tanaka Kei (Tokyo JPX), Method and apparatus for forming bump structure used for flip-chip mounting, the bump structure and the flip-chip.
    상세보기
  14. Adamjee Waseem (Austin TX), Method for ball bumping a semiconductor device.
    상세보기
  15. Marrs Robert C. (Scottsdale AZ) Hirakawa Tadashi (Osaka JPX), Method for forming an integrated circuit package with via interconnection.
    상세보기
  16. Marrs Robert C. (Scottsdale AZ), Method for interconnection of integrated circuit chip and substrate.
    상세보기
  17. Kosaki Katsuya (Itami JPX), Method for manufacturing semiconductor device contact.
    상세보기
  18. Gupta Debabrata (Scottsdale AZ), Method of bonding a semiconductor substrate to a support substrate and structure therefore.
    상세보기
  19. Geldermans Pieter (Poughkeepsie NY) Mathad Gangadhara S. (Poughkeepsie NY), Method of fabricating a chip interposer.
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  20. Rai Akiteru (Osaka JPX) Yamamura Keiji (Nara JPX) Nukii Takashi (Nara JPX), Method of making a hybrid semiconductor device.
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  21. Arikawa Shinichiro (Suwa JPX) Murakami Hiroaki (Suwa JPX), Method of manufacturing semiconductor device terminal having a gold bump electrode.
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  22. Gupta Debabrata (Scottsdale AZ) Drye James E. (Mesa AZ), Multiple integrated circuit module which simplifies handling and testing.
    상세보기
  23. Melton Cynthia M. (Bolingbrook IL) Raleigh Carl J. (Cary IL) Scheifers Steven (Hoffman Estates IL) Beckenbaugh William (Barrington IL), Palladium-coated solder ball.
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  24. Wood Alan G. (Boise ID) Hembree David R. (Boise ID) Farnworth Warren M. (Nampa ID) Cromar Larry D. (Boise ID), Probehead for ultrasonic forging.
    상세보기
  25. Gupta Debabrata (Scottsdale AZ), Reflow of multi-layer metal bumps.
    상세보기
  26. Tazima Akira (Beppu JPX), Semiconductor device package with circuit board and resin.
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  27. Mori Miki (Kawasaki JPX) Saito Masayuki (Yokohama JPX), Semiconductor device utilizing a face-down bonding and a method for manufacturing the same.
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  28. Soga Tasao (Hitachi JPX) Goda Marahiro (Hitachi JPX) Nakano Fumio (Hitachi JPX) Kushima Tadao (Ibaraki JPX) Ushifusa Nobuyuki (Hitachi JPX) Kobayashi Fumiyuki (Sagamihara JPX) Sawahata Mamoru (Hitach, Semiconductor resin package structure.
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  29. Legg Stephen P. (Southampton TX GB2) Schrottke Gustav (Austin TX), Soldering method.
    상세보기
  30. McShane Michael B. (Austin TX) Casto James J. (Austin TX) Joiner Bennett A. (Austin TX), Thermally enhanced semiconductor device utilizing a vacuum to ultimately enhance thermal dissipation.
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이 특허를 인용한 특허 (66)

  1. Harvey, Paul Marlan, Ball grid array package construction with raised solder ball pads.
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  2. Pendse, Rajendra D., Bump-on-lead flip chip interconnection.
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  3. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
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  4. Lin, Mou-Shiung; Chou, Chiu-Ming, Chip structure.
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  5. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang; Lo, Hsin-Jung, Chip structure.
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  6. Ikeda, Ukyo; Nakamura, Masato; Yamashita, Shiro, Connection structure, power module and method of manufacturing the same.
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  7. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Cylindrical bonding structure and method of manufacture.
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  8. Patrice, Philippe; Fidalgo, Jean-Christophe; Calvas, Bernard, Device and method for making devices comprising at least a chip fixed on a support.
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  9. Iwashita, Sakan; Makino, Haruhiko; Kusano, Hidetoshi, Electronic parts mounting board and production method thereof.
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  10. Kuo, Chen-Cheng; Chuang, Chita; Lin, Tsung-Shu; Chen, Chen-Shien, Elongated bump structure in semiconductor device.
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  11. Chuang, Chita; Chen, Chen-Shien; Tseng, Ming Hung; Chuang, Yao-Chun, Elongated bump structures in package structure.
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  12. Chuang, Yao-Chun; Chuang, Chita; Tseng, Ming Hung; Chen, Chen-Shien, Elongated bump structures in package structure.
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  13. Jean Dery CA; Frank D. Egitto ; Luis J. Matienzo ; Charles Ouellet CA; Luc Ouellet CA; David L. Questad ; William J. Rudik ; Son K. Tran, Flip chip assembly.
    상세보기
  14. Pendse, Rajendra D., Flip chip interconnection having narrow interconnection sites on the substrate.
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  15. Pendse, Rajendra D., Flip chip interconnection having narrow interconnection sites on the substrate.
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  16. Degani, Yinon; Gregus, Jeffrey Alan, Flip chip metallization.
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  17. Chia, Chok J.; Low, Owai H.; Ranganathan, Ramaswamy, Insulated bonding wire for microelectronic packaging.
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  18. Chia,Chok J.; Low,Owai H.; Ranganathan,Ramaswamy, Insulated bonding wire tool for microelectronic packaging.
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  19. Sundahl, Robert C.; Wong, Kenneth, Interconnected circuit board assembly and system.
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  20. Sterrett, Terry Lee; Harries, Richard J., Interconnection designs and materials having improved strength and fatigue life.
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  21. Sterrett, Terry Lee; Harries, Richard J., Interconnection designs and materials having improved strength and fatigue life.
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  22. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
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  23. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.
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  24. Chris M. Schreiber, Metallic microstructure springs and method of making same.
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  25. Maijala, Juha; Sirviö, Petri, Method and arrangement for attaching a chip to a printed conductive surface.
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  26. Ulmer Kenneth R., Method for coupling a circuit component to a substrate.
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  27. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Method for fabricating circuit component.
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  28. Wang Tsung-Hsiung,TWX, Method for forming flip chip package utilizing cone shaped bumps.
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  29. Haim Feigenbaum ; Chris M. Schreiber, Method for joining an integrated circuit.
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  30. Sundahl,Robert C.; Wong,Kenneth, Method for manufacturing an interconnected circuit board assembly.
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  31. Tie Wang SG; Colin Chun Sing Lum SG, Method for producing a flip chip package.
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  32. Harvey, Paul Marlan, Method of ball grid array package construction with raised solder ball pads.
    상세보기
  33. Aliyu, Yakub; Chooi, Simon; Zhou, Meisheng; Sudijono, John; Gupta, Subhash; Roy, Sudipto Ranendra, Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding.
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  34. Chooi, Simon; Aliyu, Yakub; Zhou, Mei Sheng; Sudijono, John; Gupta, Subhash; Roy, Sudipto; Ho, Paul; Xu, Yi, Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding.
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  35. Chooi,Simon; Aliyu,Yakub; Zhou,Mei Sheng; Sudijono,John; Gupta,Subhash; Roy,Sudipto; Ho,Paul; Xu,Yi, Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding.
    상세보기
  36. Chooi,Simon; Aliyu,Yakub; Zhou,Mei Sheng; Sudijono,John; Gupta,Subhash; Roy,Sudipto; Ho,Paul; Yi,Xu, Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding.
    상세보기
  37. Simon Chooi SG; Yakub Aliyu SG; Mei Sheng Zhou SG; John Sudijono SG; Subhash Gupta SG; Sudipto Ranendra Roy SG; Paul Ho SG; Xu Yi SG, Method of fabricating copper metal bumps for flip-chip or chip-on-board IC bonding on terminating copper pads.
    상세보기
  38. Kazuhisa Tsunoi JP; Akira Fujii JP; Shunji Baba JP; Yoshikazu Hirano JP, Method of mounting semiconductor chip part on substrate.
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  39. Liu Hermen,TWX ; Huang Yimin,TWX, Method of testing and packaging a semiconductor chip.
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  40. Chen, Yen-Ming; Lin, Chia-Fu; Hsu, Shun-Liang; Ching, Kai-Ming; Lee, Hsin-Hui; Su, Chao-Yuan; Chen, Li-Chih, Method to improve bump reliability for flip chip device.
    상세보기
  41. Honda, Hirokazu, Multilayer interconnection board, semiconductor device having the same, and method of forming the same as well as method of mounting the semicondutor chip on the interconnection board.
    상세보기
  42. Skala Stephen L. ; Bothra Subhas ; Demuizon Emmanuel, Pad metallization over active circuitry.
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  43. Jimarez Miguel Angel ; Neira Reinaldo Anthony, Receptor pad structure for chip carriers.
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  44. Joseph A. Benenati ; Claude L. Bertin ; William T. Chen ; Thomas E. Dinan ; Wayne F. Ellis ; Wayne J. Howell ; John U. Knickerbocker ; Mark V. Pierson ; William R. Tonti ; Jerzy M. Zalesinsk, Rolling ball connector.
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  45. Lee, Wen-Chieh; Lin, Mou-Shiung; Chou, Chien-Kang; Liu, Yi-Cheng; Chou, Chiu-Ming; Lee, Jin-Yuan, Semiconductor chip with coil element over passivation layer.
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  46. Lee, Wen-Chieh; Lin, Mou-Shiung; Chou, Chien-Kang; Liu, Yi-Cheng; Chou, Chiu-Ming; Lee, Jin-Yuan, Semiconductor chip with coil element over passivation layer.
    상세보기
  47. Hiroshi Oka JP; Masaaki Hiromitsu JP, Semiconductor device and method for making the same.
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  48. Pendse, Rajendra D., Semiconductor device and method of forming bump-on-lead interconnection.
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  49. Pendse, Rajendra D., Semiconductor device and method of forming bump-on-lead interconnection.
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  50. Pendse, Rajendra D., Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate.
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  51. Pendse, Rajendra D., Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask.
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  52. Pendse, Rajendra D., Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask.
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  53. Pendse, Rajendra D., Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask.
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  54. Pendse, Rajendra D., Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask.
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  55. Pendse, Rajendra D., Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask.
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  56. Ikegami, Gorou, Semiconductor device having dispersed filler between electrodes.
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  57. Archer, John, Solder bumped substrate for a fine pitch flip-chip integrated circuit package.
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  58. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection.
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  59. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection.
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  60. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection.
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  61. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection having relief structure.
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  62. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection having relief structure.
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  63. Pendse, Rajendra D.; Kim, KyungOe; Kang, TaeWoo, Solder joint flip chip interconnection having relief structure.
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  64. Belke ; Jr. Robert Edward ; Hayden Brian John ; Pham Cuong Van ; Nuno Rosa Lynda ; Todd Michael George, Solderless flip-chip assembly and method and material for same.
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  65. Kok, Chi Wah; Tam, Yee Ching, Substrate and process for semiconductor flip chip package.
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  66. Shimodaira, Tomoyuki, Terminal structure and wiring substrate.
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