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Method of and apparatus for dealing with processor abnormality in multiprocessor system 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-011/00
출원번호 US-5367395 (1995-09-29)
우선권정보 JP-0235422 (1994-09-29)
발명자 / 주소
  • Kizuka Yoshitaka,JPX
출원인 / 주소
  • Fujitsu Limited, JPX
대리인 / 주소
    Staas & Halsey
인용정보 피인용 횟수 : 31  인용 특허 : 9

초록

A multiprocessor system has processors for processing distributed works, a monitoring facility for detecting an abnormality in any one of the processors, an administration facility for providing information about the abnormal processor and information about a redundant processor, and a work allocati

대표청구항

[ I claim:] [1.] In a multiprocessor system having processors for processing distributed processes, a monitoring facility for detecting an abnormality in any one of the processors, an administration facility for providing information about an abnormal processor and information about a redundant proc

이 특허에 인용된 특허 (9)

  1. Budde David L. (Portland OR) Carson David G. (Hillsboro OR) Cornish Anthony L. (Essex OR GB2) Johnson David B. (Portland OR) Peterson Craig B. (Portland OR), Apparatus for redundant operation of modules in a multiprocessing system.
  2. Evans Colin (Stevenage GB2), Array processor with stand-by for replacing failed section.
  3. Saporito James (Stamford CT) Gaertner Wolfgang W. (Utica NY), Equipment self-repair by adaptive multifunction modules.
  4. Dahbura Anton T. (Bedminster NJ) Hery William J. (Mendham NJ) Sabnani Krishan K. (Berkeley Heights NJ), Method of spare capacity use for fault detection in a multiprocessor system.
  5. Ely Thomas C. (Bridgewater NJ), Methods and apparatus for efficient resource allocation.
  6. Chao Ming-Te (Edison NJ), Methods and apparatus for fault recovery.
  7. Glider Joseph S. (Palo Alto CA) Jaffe David H. (Belmont CA), Resource management in a multiple resource system.
  8. Elrod Steven E. (Auburn WA), Segmentable parallel bus for multiprocessor computer systems.
  9. Goodwin Paul G. (Princeton NJ) Silverman Michael B. (Lakehurst NJ) Beck George A. (Princeton NJ), Spacecraft autonomous redundancy control.

이 특허를 인용한 특허 (31)

  1. Whinnett, Nicholas William; Somerville, Fiona Clare Angharad, Accessing a base station.
  2. Mitsuhashi, Kenji; Takajitsuko, Ryo; Mitsuze, Kiyohumi, Active/standby dual apparatus and highway interface circuit for interfacing clock from highway.
  3. Hamilton, II, Rick Allen; Seaman, James Wesley, Automated processor reallocation and optimization between logical partitions.
  4. LeCren,Andrew Thomas, Dynamic reallocation of processing resources for redundant functionality.
  5. Whinnett, Nick; Somerville, Fiona, Femtocell access control.
  6. Whinnett, Nick; Somerville, Fiona; Smart, Christopher, Femtocell base station.
  7. Smart, Christopher Brian, Filter.
  8. Caudrelier,Christian; Olivares,Lorenzo; Reix,Tony, Management system for multimodule multiprocessor machines.
  9. Christian,Caudrelier; Lorenzo,Olivares; Tony,Reix, Management system for multimodule multiprocessor machines.
  10. Tu, Steven; Nguyen, Hang, Method and apparatus for machine check abort handling in a multiprocessing system.
  11. Tu,Steven; Nguyen,Hang, Method and apparatus for machine check abort handling in a multiprocessing system.
  12. Whinnett, Nicholas William, Method and device in a communication network.
  13. Whinnett, Nicholas William, Method and device in a communication network.
  14. Whinnett, Nicholas William, Method and device in a communication network.
  15. Whinnett, Nicholas William, Method and device in a communication network.
  16. Bealkowski Richard ; Bland Patrick Maurice, Method and system for hot-plugging a processor into a data processing system.
  17. Helmich, Ulrich; Kohler, Andreas; Oakes, Kenneth J.; Taubert, Martin; Trotter, John S., Method and system to execute recovery in non-homogenous multi processor environments.
  18. Whinnett, Nick, Methods and devices for reducing interference in an uplink.
  19. Fukuzumi, Norihiko; Hataida, Makoto; Okada, Seishi; Takahashi, Jin, Node, arithmetic processing device, and arithmetic processing method.
  20. Smart, Christopher Brian, Power control.
  21. Klarer,Paul R.; Hayward,David R.; Amai,Wendy A., Practical, redundant, failure-tolerant, self-reconfiguring embedded system architecture.
  22. Fukuda, Kazuhisa, Processor and method of controlling execution of processes.
  23. Fukuda, Kazuhisa, Processor and method of controlling execution of processes.
  24. Fukuda, Kazuhisa, Processor and method of controlling execution of processes.
  25. Fukuda, Kazuhisa, Processor and method of controlling execution of processes.
  26. Claydon, Anthony Peter John; Claydon, Anne Patricia, Processor architecture with switch matrices for transferring data along buses.
  27. Robbins, William; Davison, Michael; Howell, Simon; Claydon, Anthony Peter John, Processor array.
  28. Zorek, Sr., Edward Victor; Fox, Thomas James; Kern, Eric Richard; Rollins, Michael Scott; Schwartz, William Bradley, System and method for predictive processor failure recovery.
  29. Zorek, Sr.,Edward Victor; Fox,Thomas James; Kern,Eric Richard; Rollins,Michael Scott; Schwartz,William Bradley, System and method for predictive processor failure recovery.
  30. Hawkins, Peter A.; Clark, Clyde S., System with redundant central management controllers.
  31. Yuge Toshimichi,JPX ; Amemiya Toshihiro,JPX ; Matsumoto Satoshi,JPX ; Suzuki Yasuhiro,JPX, Work inheriting system.
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