이 특허를 인용한 특허 (75)

1. Nowak Edward D. ; Bothra Subhas, Apparatus for automated pillar layout.

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2. Ahn, Kie Y.; Forbes, Leonard, Bipolar transistors with low-resistance emitter contacts.

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3. Ahn, Kie Y.; Forbes, Leonard, Bipolar transistors with low-resistance emitter contacts.

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4. Ahn,Kie Y.; Forbes,Leonard, Bipolar transistors with low-resistance emitter contacts.

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5. Farrar,Paul A.; Geusic,Joseph, Buried conductor patterns formed by surface transformation of empty spaces in solid state materials.

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6. Li, Delin, Circuit board and a method for making the same.

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7. Farrar,Paul A., Coating of copper and silver air bridge structures to improve electromigration resistance and other applications.

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8. Farrar,Paul A., Coating of copper and silver air bridge structures to improve electromigration resistance and other applications.

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9. Yang, Xiaomin; Eckert, Andrew Robert, Electron beam lithography method for plating sub-100 nm trenches.

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10. Ahn, Kie Y.; Forbes, Leonard, Films deposited at glancing incidence for multilevel metallization.

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11. Ahn,Kie Y.; Forbes,Leonard, Films deposited at glancing incidence for multilevel metallization.

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12. Ahn,Kie Y.; Forbes,Leonard, Films deposited at glancing incidence for multilevel metallization.

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13. Deligianni, Hariklia; Huang, Qiang; Hummel, John P.; Romankiw, Lubomyr T.; Rothwell, Mary B., Formation of vertical devices by electroplating.

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14. Deligianni, Hariklia; Huang, Qiang; Hummel, John P.; Romankiw, Lubomyr T.; Rothwell, Mary B., Formation of vertical devices by electroplating.

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15. Noble, Wendell P.; Forbes, Leonard, Highly conductive composite polysilicon gate for CMOS integrated circuits.

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16. Wendell P. Noble ; Leonard Forbes, Highly conductive composite polysilicon gate for CMOS integrated circuits.

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17. Doyle, Matthew S.; Kuczynski, Joseph; Mann, Phillip V.; O'Connell, Kevin M., Implementing backdrilling elimination utilizing anti-electroplate coating.

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18. Doyle, Matthew S.; Kuczynski, Joseph; Mann, Phillip V.; O'Connell, Kevin M., Implementing backdrilling elimination utilizing anti-electroplate coating.

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19. Ahn, Kie Y., Integrated circuit wiring with low RC time delay.

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20. Berthold,J철rg; Schwarzl,Siegfried, Integrated electrical circuit and method for fabricating it.

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21. Rohini Gupta ; John D. Tauke, Interdigitated capacitor structure for use in an integrated circuit.

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22. Buynoski Matthew S., Low dielectric semiconductor device with rigid lined interconnection system.

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23. Buynoski Matthew S., Low dielectric semiconductor device with rigid, conductively lined interconnection system.

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24. Geusic, Joseph E.; Farrar, Paul A.; Bhattacharyya, Arup, Low k interconnect dielectric using surface transformation.

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25. Geusic,Joseph E.; Farrar,Paul A.; Bhattacharyya,Arup, Low k interconnect dielectric using surface transformation.

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26. Choi,Seung Man; Park,Ki Chul; Suh,Bong Seok; Kim,Il Ryong, Metal-insulator-metal (MIM) capacitor and method of fabricating the same.

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27. Jiang Linda (Tong) ; Hymes Diane J., Method and apparatus for cleaning low K dielectric and metal wafer surfaces.

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28. Jiang Linda ; Hymes Diane J., Method and apparatus for cleaning low K dielectric and metal wafer surfaces.

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29. Wu Hua-Shu,TWX ; Peng Chun-Hung,TWX, Method for forming via holes.

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30. Sekiguchi Mitsuru,JPX, Method for making semiconductor device containing low carbon film for interconnect structures.

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31. Horak, David Vaclav; Koburger, III, Charles William; Mitchell, Peter H.; Nesbit, Larry Alan, Method for manufacturing a multi-level interconnect structure.

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32. Kumar, Devendra, Method for manufacturing semiconductor device having porous structure with air-gaps.

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33. Wu Juan-Yuan,TWX ; Lur Water,TWX, Method of applying partial reverse mask.

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34. Ahn,Kie Y., Method of fabricating a semiconductor interconnect structure.

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35. Sakamoto, Kazuyuki, Method of fabricating an air bridge.

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36. Zhao,Bin, Method of fabricating an interconnect structure employing air gaps between metal lines and between metal layers.

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37. Park, Stephen Keetai, Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer.

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38. Park Stephen Keetai, Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer and an unconstrained copper anneal.

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39. Geusic,Joseph E.; Marsh,Eugene P., Method of forming mirrors by surface transformation of empty spaces in solid state materials.

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40. Geusic,Joseph E.; Marsh,Eugene P., Method of forming mirrors by surface transformation of empty spaces in solid state materials.

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41. Geusic,Joseph E.; Marsh,Eugene P., Method of forming mirrors by surface transformation of empty spaces in solid state materials and structures thereon.

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42. Wong,Lawrence D.; Leu,Jihperng; Kloster,Grant; Ott,Andrew; Morrow,Patrick, Method of making semiconductor device using a novel interconnect cladding layer.

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43. Lin, Charles W. C., Method of manufacturing a multilayer interconnect substrate.

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44. Ahn, Kie Y.; Forbes, Leonard; Farrar, Paul A., Methods and structures for metal interconnections in integrated circuits.

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45. Ahn, Kie Y.; Forbes, Leonard; Farrar, Paul A., Methods and structures for metal interconnections in integrated circuits.

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46. Ahn,Kie Y.; Forbes,Leonard; Farrar,Paul A., Methods and structures for metal interconnections in integrated circuits.

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47. Forbes, Leonard; Farrar, Paul A.; Ahn, Kie Y., Methods and structures for silver interconnections in integrated circuits.

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48. Eldridge, Jerome M.; Farrar, Paul A., Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture.

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49. Eldridge, Jerome M.; Farrar, Paul A., Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture.

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50. Eldridge, Jerome M.; Farrar, Paul A., Microelectronic device package with conductive elements and associated method of manufacture.

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51. Eldridge, Jerome M.; Farrar, Paul A., Microelectronic device with package with conductive elements and associated method of manufacture.

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52. Kevin S. Petrarca ; Rebecca D. Mih, Microprocessor having air as a dielectric and encapsulated lines.

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53. Babich, Katherina E.; Carruthers, Roy Arthur; Dalton, Timothy Joseph; Grill, Alfred; Hedrick, Jeffrey Curtis; Jahnes, Christopher Vincent; Mays, Ebony Lynn; Perraud, Laurent; Purushothaman, Sampath; , Multilayer interconnect structure containing air gaps and method for making.

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54. Babich,Katherina E.; Carruthers,Roy Arthur; Dalton,Timothy Joseph; Grill,Alfred; Hedrick,Jeffrey Curtis; Jahnes,Christopher Vincent; Mays,Ebony Lynn; Perraud,Laurent; Purushothaman,Sampath; Saenger,K, Multilayer interconnect structure containing air gaps and method for making.

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55. Ahn,Kie Y.; Forbes,Leonard, Multilevel interconnect structure with low-k dielectric.

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56. Makoto Sasaki JP, Multilevel interconnection structure having an air gap between interconnects.

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57. Sasaki Makoto,JPX, Multilevel interconnection structure having an air gap between interconnects.

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58. Ghoshal Uttam Shyamalindu, Practical air dielectric interconnections by post-processing standard CMOS wafers.

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59. Romankiw, Lubomyr Taras, Process for making low dielectric constant hollow chip structures by removing sacrificial dielectric material after the chip is joined to a chip carrier.

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60. Or-Bach Zvi ; Cox Bill Douglas, Semiconductor device.

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61. Zvi Or-Bach ; Bill Douglas Cox, Semiconductor device.

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62. Sekiguchi, Mitsuru, Semiconductor device and method for fabricating the same.

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63. Kakuhara, Yumi, Semiconductor device and method of its fabrication.

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64. Tamio Satou JP, Semiconductor device including lead wiring protected by dual barrier films.

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65. Su, Shu-Hui; Huang, Cheng-Lin; Yang, Jiing-Feng; Wu, Zhen-Cheng; Wu, Ren-Guei; Chen, Dian-Hau; Mii, Yuh-Jier, Semiconductor structure having an air-gap region and a method of manufacturing the same.

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66. Su, Shu-Hui; Huang, Cheng-Lin; Yang, Jiing-Feng; Wu, Zhen-Cheng; Wu, Ren-Guei; Chen, Dian-Hau; Mii, Yuh-Jier, Semiconductor structure having an air-gap region and a method of manufacturing the same.

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67. Lichter, Gerd, Semiconductor structure having an interconnect and method of producing the semiconductor structure.

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68. Gotkis,Yehiel; Wei,David; Kistler,Rodney, Semiconductor structure implementing low-K dielectric materials and supporting stubs.

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69. Smith, Kenneth H.; Rizzo, Nicholas D.; Aggarwal, Sanjeev; Ciancio, Anthony; Butcher, Brian R.; Kyler, Kelly Wayne, Structure and method for fabricating cladded conductive lines in magnetic memories.

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70. Keith Brankner ; Kenneth D. Brennan ; Yvette Shaw, Technique for intralevel capacitive isolation of interconnect paths.

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71. Moslehi Mehrdad M., Ultra high-speed chip interconnect using free-space dielectrics.

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72. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.

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73. Ohtani, Hisashi; Yamazaki, Shunpei, Wiring line and manufacture process thereof and semiconductor device and manufacturing process thereof.

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74. Ohtani, Hisashi; Yamazaki, Shunpei, Wiring line and manufacture process thereof, and semiconductor device and manufacturing process thereof.

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75. Ohtani,Hisashi; Yamazaki,Shunpei, Wiring line and manufacture process thereof, and semiconductor device and manufacturing process thereof.

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