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특허 상세정보

MyON담기
내보내기 페이스북 공유 카카오톡 공유

Method of making non-volatile memory device having a floating gate with enhanced charge retention

특허상세정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) H01L-021/8247   
미국특허분류(USC) 438/261 ; 438/763 ; 438/910
출원번호 US-0393138 (1995-02-21)
발명자 / 주소
출원인 / 주소
대리인 / 주소
    Daffer
인용정보 피인용 횟수 : 59  인용 특허 : 19
초록
▼

A non-volatile memory device is fabricated having enhanced charge retention capability. Enhanced charge retention is achieved upon the floating gate of the non-volatile memory device. The floating gate maybe can configured as a stacked or non-stacked pair of polysilicon conductors. In either instance, negative charge programmed upon the floating gate is retained by reducing the presence of positively charged atoms within dielectrics overlying the floating gate conductor. Moreover, diffusion avenues of the positively charged hydrogen are reduced by mainta...

대표
청구항

[ What is claimed is:] [1.] A method for fabricating a memory device having a floating gate, comprising the steps of:providing a semiconductor substrate upon which a tunnel oxide is formed;depositing a floating gate upon said tunnel oxide; andforming at an elevational level above said floating gate a hydrogen-containing dielectric having bonded hydrogen which remains in its bonded location during formation of said hydrogen-containing dielectric and further remains in its bonded location after electrons are injected upon said floating gate.

이 특허에 인용된 특허 (19)

  1. Amin Alaaeldin (Dhahran SAX). Architecture for a flash erase EEPROM memory. USP1991034999812.
  2. Kazerounian Reza (Alameda CA) Eitan Boaz (Sunnyvale CA) Irani Rustom F. (Santa Clara CA). EPROM virtual ground array. USP1992095151375.
  3. Arima Hideaki (Hyogo JPX) Okumura Yoshinori (Hyogo JPX) Genjo Hideki (Hyogo JPX) Ogoh Ikuo (Hyogo JPX) Yuzuriha Kohjiroh (Hyogo JPX) Nakashima Yuichi (Hyogo JPX). Electrically programmable non-volatile memory device and manufacturing method thereof. USP1992035101250.
  4. Mitchell Allan T. (Garland TX) Riemenschneider Bert R. (Murphy TX). Fabricating a single level merged EEPROM cell having an ONO memory stack substantially spaced from the source region. USP1992065120672.
  5. Van Buskirk Michael A. (San Jose CA) Plouse Kevin W. (San Jose CA) Pawletko Joseph G. (Sunnyvale CA) Chang Chi (Redwood City CA) Haddad Sameer S. (San Jose CA) Gutala Ravi P. (Sunnyvale CA). Flash EEPROM array with high endurance. USP1994085335198.
  6. Haddad Sameer S. (San Jose CA) Chang Chi (Redwood City CA) Matalvo Antonio (San Francisco CA) Van Buskirk Michael A. (San Jose CA). Flash EEPROM array with negative gate voltage erase operation. USP1991125077691.
  7. Kressel Henry (Elizabeth NJ) Hsu Sheng T. (Lawrenceville NJ). Memory array with redundant elements. USP1983124422161.
  8. Crotti Pier L. (Landriano ITX). Method for fabricating memory cell matrix having parallel source and drain interconnection metal lines formed on the sub. USP1994015279982.
  9. Choi Jeong-hyeok (Seoul KRX) Kim Geon-su (Kyunggi KRX) Sin Yun-seong (Kyunggi KRX). Method of making a nonvolatile semiconductor memory device. USP1993055208175.
  10. Sethi Rakesh B. (Campbell CA). Method of making a split floating gate EEPROM cell. USP1994025284786.
  11. Yuan Jack H. (Cupertino CA) Harari Eliyahou (Los Gatos CA). Method of making dense flash EEprom semiconductor memory structures. USP1991125070032.
  12. Mikata Yuuichi (Yokohama JPX) Usami Toshiro (Yokohama JPX). Method of manufacturing a semiconductor memory device having a floating gate electrode composed of 2-10 silicon grains. USP1992095149666.
  13. Sakagami Eiji (Kawasaki JPX). Method of manufacturing semiconductor device by controlling the profile of the density of p-type impurities in the sourc. USP1992095147811.
  14. Fukatsu Shigemitsu (Okazaki JPX) Asai Akiyoshi (Nisshin JPX). Method of reducing the trap density of an oxide film for application to fabricating a nonvolatile memory cell. USP1994015279981.
  15. Chen Zhizhang (Duluth GA) Rohatgi Ajeet (Marietta GA). Methods for passivating silicon devices at low temperature to achieve low interface state density and low recombination. USP1995105462898.
  16. Chang Chi (Redwood City CA). One transistor flash EPROM cell. USP1990094958321.
  17. Tsubouchi Kazuo (Sendai JPX) Masu Kazuya (Sendai JPX). Process for non-selectively forming deposition film on a non-electron-donative surface. USP1994115364664.
  18. Tang Daniel N. (San Jose CA) Lu Wen-Juei (Sunnyvale CA). Process for self aligning a source region with a field oxide region and a polysilicon gate. USP1992065120671.
  19. Takasaki Kanetake (Tokyo JPX) Takagi Mikio (Kawasaki JPX) Koyama Kenji (Yokosuka JPX). UV erasable EPROM with UV transparent silicon oxynitride coating. USP1986044581622.

이 특허를 인용한 특허 피인용횟수: 59

  1. Dadashev, Oleg; Betser, Yoram; Maayan, Eduardo. Apparatus and methods for multi-level sensing in a memory array. USP2009057532529.
  2. Kushnarenko, Alexander. Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same. USP2012088253452.
  3. Shappir, Assaf. Contact in planar NROM technology. USP2011118053812.
  4. Bloom, Ilan; Eitan, Boaz; Irani, Rustom. Dense non-volatile memory array and method of fabrication. USP2010087786512.
  5. Irani, Rustom; Eitan, Boaz; Bloom, Ilan; Shappir, Assaf. Double density NROM with nitride strips (DDNS). USP2009127638835.
  6. Sofer,Yair; Maayan,Eduardo; Betser,Yoram. Dynamic matching of signal path and reference path for sensing. USP2008127466594.
  7. Maayan, Eduardo; Eliyahu, Ron; Eitan, Boaz. EEPROM array and method for operation thereof. USP2009047518908.
  8. Han, Kim-Kwong Michael; Derhacobian, Narbeh; Raszka, Jaroslav. Electrically-alterable non-volatile memory cell. USP2004096788574.
  9. Han,Kim Kwong Michael; Derhacobian,Narbeh; Raszka,Jaroslav. Electrically-alterable non-volatile memory cell. USP2006087095076.
  10. Dvir, Ran; Cohen, Zeev. High voltage insertion in flash memory cards. USP2004116826107.
  11. Betser, Yoram; Kushnarenko, Alexander; Dadashev, Oleg. Measuring and controlling current consumption and output current of charge pumps. USP2009107605579.
  12. Polansky, Yan; Lavan, Avi. Memory array programming circuit and a method for using the circuit. USP2010067743230.
  13. Raszka, Jaroslav; Tiwari, Vipin Kumar. Memory cell sensing with low noise generation. USP2005026850446.
  14. Raszka,Jaroslav; Tiwari,Vipin Kumar. Memory cell sensing with low noise generation. USP2007027184346.
  15. Weber David M.. Method and apparatus for maintaining test data during fabrication of a semiconductor wafer. USP2001086274395.
  16. Dadashev,Oleg. Method and apparatus for measuring charge pump output current. USP2007057221138.
  17. Eitan Boaz,ILX ; Rotstein Israel,ILX. Method for creating diffusion areas for sources and drains without an etch step. USP2000106133095.
  18. Maayan, Eduardo; Eitan, Boaz; Lann, Ameet. Method for programming a reference cell. USP2010047701779.
  19. Maayan, Eduardo; Eliyahu, Ron; Lann, Ameet; Eitan, Boaz. Method for programming a reference cell. USP2003066584017.
  20. Maayan,Eduardo; Eliyahu,Ron; Lann,Ameet; Eitan,Boaz. Method for programming a reference cell. USP2006067064983.
  21. Lusky, Eli; Eitan, Boaz. Method of erasing non-volatile memory cells. USP2010027668017.
  22. Lee Keun Woo,KRX ; Kim Ki Seog,KRX ; Shin Jin,KRX ; Park Sung Kee,KRX. Method of forming a gate in a stack gate flash EEPROM cell. USP2001036204125.
  23. Kent Kuo-Hua Chang TW; Cheng-Chen Calvin Hsueh TW. Method to improve nitride floating gate charge trapping for NROM flash memory device. USP2002096444521.
  24. Eitan, Boaz; Shainsky, Natalie. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection. USP2010047692961.
  25. Shappir,Assaf; Eisen,Shai. Method, circuit and systems for erasing one or more non-volatile memory cells. USP2008057369440.
  26. Cohen, Guy; Polansky, Yan. Method, system and circuit for programming a non-volatile memory array. USP2010037675782.
  27. Cohen,Guy. Method, system, and circuit for operating a non-volatile memory array. USP2008047352627.
  28. Shappir,Assaf; Avni,Dror; Eitan,Boaz. Method, system, and circuit for operating a non-volatile memory array. USP2008097420848.
  29. Raszka,Jaroslav. Methods and apparatuses for a dual-polarity non-volatile memory cell. USP2006107130213.
  30. Raszka,Jaroslav. Methods and apparatuses for a sense amplifier. USP2008047355914.
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  32. Shubat,Alexander; Raszka,Jaroslav. Methods and apparatuses for test circuitry for a dual-polarity non-volatile memory cell. USP2006016992938.
  33. Boaz Eitan IL. NROM cell with generally decoupled primary and secondary injection. USP2002086429063.
  34. Eitan, Boaz. NROM cell with self-aligned programming and erasure areas. USP2003126664588.
  35. Eitan, Boaz; Shainsky, Natalie. NROM non-volatile memory and mode of operation. USP2010077760554.
  36. Eitan, Boaz. Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping. USP2003046552387.
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  39. Eitan,Boaz. Non-volatile memory cell and non-volatile memory devices. USP2008077405969.
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  44. Shappir,Assaf; Eisen,Shai. Partial erase verify. USP2008127468926.
  45. He Yue-song ; Chang Kent K. ; Huang Allen U.. Process to reduce post cycling program VT dispersion for NAND flash memory devices. USP2001096284602.
  46. Avni, Dror; Eitan, Boaz. Programming and erasing methods for a non-volatile memory cell. USP2005086937521.
  47. Avni, Dror; Eitan, Boaz. Programming and erasing methods for a non-volatile memory cell. USP2005086928001.
  48. Ilan Bloom IL; Eduardo Maayan IL; Boaz Eitan IL. Programming and erasing methods for a reference cell of an NROM array. USP2002126490204.
  49. Bloom, Ilan; Eitan, Boaz; Cohen, Zeev; Finzi, David; Maayan, Eduardo. Programming of nonvolatile memory cells. USP2004126829172.
  50. Lusky,Eli; Bloom,Ilan; Shappir,Assaf; Eitan,Boaz. Protection of NROM devices from charge damage. USP2008017317633.
  51. Bloom, Iian; Eitan, Boaz. Protective layer in memory device and method therefor. USP2004126828625.
  52. Bloom,Ilan; Ettan,Boaz. Protective layer in memory device and method therefor. USP2006087098107.
  53. Eitan, Boaz. Reducing secondary injection effects. USP2003066583007.
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  55. Ishikawa Hiraku,JPX. Semiconductor device using a thermal treatment of the device in a pressurized steam ambient as a planarization technique. USP2001116319847.
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