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Memory system having programmable control parameters 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-008/00
출원번호 US-0508828 (1995-07-28)
발명자 / 주소
  • Roohparvar Frankie F.
  • Rinerson Darrell D.
  • Chevallier Christophe J.
  • Briner Michael S.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg, Woessner & Kluth, P.A.
인용정보 피인용 횟수 : 162  인용 특허 : 16

초록

A memory system capable of being configured for optimum performance after fabrication using control parameters stored in non-volatile data storage units. The system includes an array of memory cells, separate from the data storage units, arranged in a multiplicity of rows and a multiplicity of colum

대표청구항

[ It is claimed:] [1.] A memory system comprising:an array of memory cells arranged in a multiplicity of rows and a multiplicity of columns, with each cell located in one of the rows and one of the columns;a memory controller, operably coupled to the array, said memory controller configured to contr

이 특허에 인용된 특허 (16)

  1. Roohparvar Frankie F. (Cupertino CA), Apparatus for entering and executing test mode operations for memory.
  2. Fandrich Mickey L. (Placerville CA) Yarlagadda Chakravarthy (Citrus Heights CA) Rozman Rodney R. (Placerville CA) Gould Geoffrey A. (El Dorado Hills CA), Block specific status information in a memory device.
  3. Fandrich Mickey L. (Placerville CA), Boundary test scheme for an intelligent device.
  4. Kynett Virgil N. (El Dorado Hills CA) Fandrich Mickey L. (Placerville CA), Circuitry and method for selectively protecting the integrity of data stored within a range of addresses within a non-vo.
  5. Fandrich Mickey L. (Placerville CA) Lee Kelvin W. (Sacramento CA) Kreiffels Jerry A. (Citrus Heights CA) Kynett Virgil N. (El Dorado Hills CA) Robinson Kurt B. (Newcastle CA), Command interface between user commands and a memory device.
  6. Tabata Junichi (Tokyo JPX), Detecting circuit for a power source voltage.
  7. Kynett Virgil N. (El Dorado Hills CA) Fandrich Mickey L. (Placerville CA) Wells Steven E. (Citrus Heights CA) Robinson Kurt B. (Newcastle CA) Jungroth Owen W. (Sonora CA), Flash memory blocking architecture.
  8. Hazen Peter K. (Sacramento CA) Talreja Sanjay S. (Citrus Heights CA) Sweha Sherif R. B. (El Dorado Hills CA), Floating gate nonvolatile memory with configurable erasure blocks.
  9. Mills Duane F. (Sacramento CA) Javanifard Jahanshir J. (Sacramento CA) Rozman Rodney R. (Placerville CA) Frary Kevin W. (Fair Oaks CA) Sweha Sherif R. B. (El Dorado Hills CA), Memory device having selectable number of output pins.
  10. Roohparvar Frankie F. (Cupertino CA), Memory system having non-volatile data storage structure for memory control parameters and method.
  11. Roohparvar Frankie F. (Cupertino CA) Chevallier Christophe J. (Palo Alto CA), Memory system having programmable flow control register.
  12. Fandrich Mickey L. (Placerville CA) Durante Richard J. (Citrus Heights CA) Underwood Keith F. (Orangevale CA) Rozman Rodney R. (Placerville CA), Method and apparatus for execution of operations in a flash memory array.
  13. Nagai Nobutaka (Tokyo JPX), Power-on reset circuit device for multi-level power supply sources.
  14. Frisch Anthony E. (Kokomo IN) Stringfellow David W. (Kokomo IN), Power-on-reset (POR) circuit having power supply rise time independence.
  15. Moyal Miki (Austin TX), Trimming circuit.
  16. Kokubo Nobuyuki (Hyogo JPX) Ikeda Kazuya (Hyogo JPX), Voltage level detecting circuit.

이 특허를 인용한 특허 (162)

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