초록 ▼

A bus bridge circuit employs a dynamic allocation scheme that allows read transactions to be pipelined without deadlock and without the need for permanently reserving multiple buffer slots for read response transactions. The bus bridge circuit associates input and output buffers with a node and incl

A bus bridge circuit employs a dynamic allocation scheme that allows read transactions to be pipelined without deadlock and without the need for permanently reserving multiple buffer slots for read response transactions. The bus bridge circuit associates input and output buffers with a node and includes a state machine to monitor the number and type of transaction packets currently in slots that make up the buffers. In particular, the state machine monitors the number of transaction packets loaded in the output buffer slots, the number of outstanding read transactions for the node, and the number of read response transactions currently loaded in the output buffer. The state machine then allows the node to load a READ or WRITE transaction only if the monitored data indicates at least one of the buffer slots will be available to service a READ RESPONSE subsequently loaded by the node. The state machine launches READs to the node only when an unallocated buffer slot is available to service the corresponding READ RESPONSE.

대표청구항 ▼

[ What is claimed is:] [1.] A bridge circuit for transmitting message packets between a first and second node in a system employing a packet switched, split transaction bus protocol, the bridge circuit comprising:first and second buffers, each buffer having an input line, an output line and a number

[ What is claimed is:] [1.] A bridge circuit for transmitting message packets between a first and second node in a system employing a packet switched, split transaction bus protocol, the bridge circuit comprising:first and second buffers, each buffer having an input line, an output line and a number of buffer slots for temporarily storing message packets; anda first state machine coupled to the first node, to the input line of the first buffer and to the output line of the second buffer, the first state machine including a first counter for monitoring outstanding read transactions launched to the first node, a second counter for monitoring read response transactions loaded into the first buffer by the first node, and a third counter for monitoring currently loaded buffer slots of the first buffer, the first state machine including logic for transferring transactions to and from the first node according to launch and load slot availability criteria determined from the first, second, and third counters; anda second state machine coupled to the second node, to the input line of the second buffer, and to the output line of the second buffer, the second state machine including a first counter for monitoring outstanding read transactions launched to the second node, a second counter for monitoring read response transactions loaded into the second buffer by the second node, and a third counter for monitoring currently loaded buffer slots of the second buffer, the second state machine also including logic for transferring transactions to and from the second node according to launch and load slot availability criterion determined from the first, second, and third counters.