초록 ▼

A method and apparatus for automatically generating test patterns for a circuit design using a number of data processing elements. The present invention reduces the wall time required to generate the test patterns for the overall circuit design by partitioning the design into a number of partitions,

A method and apparatus for automatically generating test patterns for a circuit design using a number of data processing elements. The present invention reduces the wall time required to generate the test patterns for the overall circuit design by partitioning the design into a number of partitions, distributing the partitions to a number of data processing elements, and generating test patterns for each partition on the corresponding data processing elements. The present invention automatically assembles the resulting local test patterns to reflect the scan structure of the overall circuit design.

대표청구항 ▼

[ What is claimed is:] [1.] A method for generating a number of test patterns for a circuit design, wherein each of the number of test patterns include a number of test bits, the circuit design having a number of controllable locations and a number of observable locations wherein selected ones of th

[ What is claimed is:] [1.] A method for generating a number of test patterns for a circuit design, wherein each of the number of test patterns include a number of test bits, the circuit design having a number of controllable locations and a number of observable locations wherein selected ones of the number of controllable and observable locations corresponds to one of the number of test bits of each of the number of test patterns, the test patterns being generated on a number of data processing elements including a master data processing element, the method comprising the steps of:a. partitioning the circuit design into a number of partitions using the master data processing element, wherein each of the number of partitions include selected ones of the number of controllable and observable locations;b. sending a first selected set of the number of partitions to a first one of the number of data processing elements;c. sending a second selected set of the number of partitions to a second one of the number of data processing elements;d. generating a number of first local test patterns for the first selected set of the number of partitions on the first one of the number of data processing elements, wherein each of the number of first local test patterns include a number of first local test bits, and each of the first local test bits correspond to a selected one of the number of controllable and observable locations that are associated with the first selected set of the number of partitions;e. generating a number of second local test patterns for the second selected set of the number of partitions on the second one of the number of data processing elements, wherein each of the number of second local test patterns include a number of second local test bits, and each of the second local test bits correspond to a selected one of the number of controllable and observable locations that are associated with the second selected set of the number of partitions; andf. merging the number of first local test patterns and the number of second local test patterns to provide selected ones of the number of test patterns for the circuit design.