초록 ▼

A method and apparatus for use in computer systems utilizes a memory chip employing multiple distributed SRAM caches directly linked to a single DRAM main memory block. Each cache is directly linked to a different bus. Each chip further contains a partially distributed arbitration and control circui

A method and apparatus for use in computer systems utilizes a memory chip employing multiple distributed SRAM caches directly linked to a single DRAM main memory block. Each cache is directly linked to a different bus. Each chip further contains a partially distributed arbitration and control circuit for implementing cache policy and arbitrating memory refresh cycles.

대표청구항 ▼

[ We claim:] [1.] In a computer system including; a plurality of buses, each bus serving at least one device, and each bus serving to communicate direct memory access read/write requests, data, and main memory addresses, from a device to a main memory which is tightly coupled to the devices; a distr

[ We claim:] [1.] In a computer system including; a plurality of buses, each bus serving at least one device, and each bus serving to communicate direct memory access read/write requests, data, and main memory addresses, from a device to a main memory which is tightly coupled to the devices; a distributed cache memory system, comprising:a first group of one or more devices requiring direct memory access;a second group of one or more devices requiring direct memory access;a first bus connecting said first group of devices directly to the main memory;a first cache connected directly to said first bus and to the main memory;a second bus connecting said second group of devices directly to the main memory;a second cache connected directly to said second bus and to the main memory;a cache memory control and arbitration unit coupled to said first and second cache, said first and second bus, and to said main memory for processing concurrent direct memory access requests from said first and said second bus.