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Method and apparatus for performing reads of related data from a set-associative cache memory 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-001/00
출원번호 US-0785199 (1997-01-17)
발명자 / 주소
  • Rahman Monis
  • Poplingher Mircea
  • Yeh Tse-Yu
  • Chen Wenliang
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman
인용정보 피인용 횟수 : 122  인용 특허 : 7

초록

Allocation circuitry for allocating entries within a set-associative cache memory is disclosed. The set-associative cache memory comprises N ways, each way having M entries and corresponding entries in each of the N ways constituting a set of entries. The allocation circuitry has a first circuit whi

대표청구항

[ What is claimed is:] [1.] A computer-implemented method of allocating entries within a set-associative cache memory having first and second ways, each way having a plurality of entries, wherein corresponding entries of each of the first and second ways comprise respective sets ofentries, the metho

이 특허에 인용된 특허 (7)

  1. Lichy Joe (Sunnyvale CA), Hybrid write back/write through cache having a streamlined four state cache coherency protocol for uniprocessor computer.
  2. Westberg Thomas E. (Sudbury MA), Intelligent cache memory and prefetch method based on CPU data fetching characteristics.
  3. Benhase Michael T. (Tucson AZ) Duke Alan H. (Tucson AZ), Method and apparatus for converting addresses of a backing store having addressable data storage devices for accessing a.
  4. Goodwin Paul M. (Littleton MA) Thaller Kurt M. (Acton MA), Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffe.
  5. Okada Tetsuhiko (Hachioji JPX) Nishii Osamu (Inagi JPX) Takeda Hiroshi (Higashi-Yamato JPX), Method for prefetching pointer-type data structure and information processing apparatus therefor.
  6. Hatakeyama Tetsuo (Tokyo JPX), Multi-way set associative cache system in which the number of lines per set differs and loading depends on access freque.
  7. Steely ; Jr. Simon C. (Hudson NH) Sager David J. (Acton MA), Multiple block line prediction.

이 특허를 인용한 특허 (122)

  1. Abdallah, Mohammad, Accelerated code optimizer for a multiengine microprocessor.
  2. Soderquist, Peter G.; Kanapathipillai, Pradeep; Semeria, Bernard J.; de Cesare, Joshua P.; Williamson, David J.; Williams, III, Gerard R., Access permissions modification.
  3. Abdallah, Mohammad A., Apparatus and method for processing an instruction matrix specifying parallel and dependent operations.
  4. Henry, G. Glenn; McDonald, Thomas C., Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence.
  5. Flynn, David; Strasser, John; Thatcher, Jonathan, Apparatus, system, and method for a device shared between multiple independent hosts.
  6. Flynn, David; Thatcher, Jonathan, Apparatus, system, and method for a storage layer.
  7. Talagala, Nisha; Flynn, David, Apparatus, system, and method for accessing memory.
  8. Thatcher, Jonathan; Flynn, David, Apparatus, system, and method for allocating storage.
  9. Flynn, David; Uphoff, Stephan; Ouyang, Xiangyong; Nellans, David; Wipfel, Robert, Apparatus, system, and method for atomic storage operations.
  10. Flynn, David; Nellans, David; Strasser, John; Peterson, James G.; Wipfel, Robert, Apparatus, system, and method for auto-commit memory.
  11. Flynn, David; Strasser, John; Thatcher, Jonathan; Atkisson, David; Zappe, Michael; Aune, Joshua; Vigor, Kevin B., Apparatus, system, and method for caching data on a solid-state storage device.
  12. Flynn, David; Nellans, David; Ouyang, Xiangyong, Apparatus, system, and method for conditional and atomic storage operations.
  13. Flynn, David; Nellans, David; Ouyang, Xiangyong, Apparatus, system, and method for conditional and atomic storage operations.
  14. Flynn, David; Zappe, Michael; Thatcher, Jonathan, Apparatus, system, and method for coordinating storage requests in a multi-processor/multi-thread environment.
  15. Flynn, David; Atkisson, David; Dixon, Drex; Flynn, Jonathan; Hansen, Brandon, Apparatus, system, and method for data block usage information synchronization for a non-volatile storage volume.
  16. Atkisson, David; Ludwig, Jonathan, Apparatus, system, and method for destaging cached data.
  17. Flynn, David; Thatcher, Jonathan; Zappe, Michael, Apparatus, system, and method for identifying data that is no longer in use.
  18. Peterson, Jim; Talagala, Nisha; Wipfel, Robert; Atkisson, David; Ludwig, Jonathan; Martin, Ann, Apparatus, system, and method for managing a cache.
  19. Flynn, David; Thatcher, Jonathan; Zappe, Michael, Apparatus, system, and method for managing data from a requesting device with an empty data token directive.
  20. Flynn, David; Thatcher, Jonathan; Zappe, Michael, Apparatus, system, and method for managing data in a storage device with an empty data token directive.
  21. Fillingim, Jeremy, Apparatus, system, and method for managing lifetime of a storage device.
  22. Strasser, John; Flynn, David; Inskeep, Bill, Apparatus, system, and method for managing out-of-service conditions.
  23. Smith, Lance L.; Fillingim, Jeremy; Flynn, David; Inskeep, Bill; Strasser, John; Thatcher, Jonathan, Apparatus, system, and method for power reduction management in a storage device.
  24. Flynn, David; Nellans, David; Ouyang, Xiangyong, Apparatus, systems, and methods for nameless writes.
  25. Talagala, Nisha; Sundararaman, Swaminathan; Sridharan, Srinath, Auto-commit memory.
  26. Talagala, Nisha; Flynn, David, Auto-commit memory metadata and resetting the metadata by writing to special address in free space of page storing the metadata.
  27. Talagala, Nisha; Sundararaman, Swaminathan; Sridharan, Srinath, Auto-commit memory synchronization.
  28. Yokoi, Megumi, Branch prediction apparatus of computer storing plural branch destination addresses.
  29. Abdallah, Mohammad A., Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer.
  30. Ashmore, Paul Andrew; Davies, Ian Robert; Maine, Gene; Vedder, Rex Weldon, Certified memory-to-memory data transfer between active-active raid controllers.
  31. Hino, Mitsuaki; Yamazaki, Yasuhiro, Data processor and memory read active control method.
  32. Abdallah, Mohammad, Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines.
  33. Flynn, David; Talagala, Nisha, Enhanced integrity through atomic writes in cache.
  34. Hyun, Jea Woong; Nellans, David, Erase suspend/resume for memory.
  35. Abdallah, Mohammad, Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines.
  36. Abdallah, Mohammad, Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines.
  37. Grandou, Gilles Eric; Raphalen, Philippe Jean-Pierre, Handling of cache accesses in a data processing apparatus.
  38. Gelke, Hans-Joachim; Koch, Stefan; Gappisch, Steffen, Integrated circuit with flash memory including dedicated flash bus and flash bridge.
  39. Abdallah, Mohammad, Interconnect system to support the execution of instruction sequences by a plurality of partitionable engines.
  40. Flynn, David; Wipfel, Robert; Nellans, David; Strasser, John, Logical interface for contextual storage.
  41. Atkisson, David; Flynn, David, Managing cache pools.
  42. Joshi, Vikram; Luan, Yang; Apte, Manish R.; Vidwans, Hrishikesh A.; Brown, Michael F., Managing data input/output operations.
  43. Silberman Joel Abraham ; Dhong Sang Hoo, Memory circuit for reordering selected data in parallel with selection of the data from the memory circuit.
  44. Talagala, Nisha; Flynn, David, Memory device with volatile and non-volatile media.
  45. Abdallah, Mohammad, Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines.
  46. Yeh, Tse-Yu; Sharangpani, Harshvardhan P., Method and apparatus for branch prediction using first and second level branch prediction tables.
  47. Avudaiyappan, Karthikeyan; Alurkar, Sourabh, Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput.
  48. Davies, Ian Robert; Pecone, Victor Key, Method for adopting an orphan I/O port in a redundant storage controller.
  49. Abdallah, Mohammad, Method for dependency broadcasting through a block organized source view data structure.
  50. Abdallah, Mohammad, Method for dependency broadcasting through a source organized source view data structure.
  51. Abdallah, Mohammad, Method for emulating a guest centralized flag architecture by using a native distributed flag architecture.
  52. Abdallah, Mohammad, Method for executing multithreaded instructions grouped into blocks.
  53. Abdallah, Mohammad, Method for executing multithreaded instructions grouped into blocks.
  54. Abdallah, Mohammad, Method for implementing a reduced size register view data structure in a microprocessor.
  55. Abdallah, Mohammad A., Method for implementing a reduced size register view data structure in a microprocessor.
  56. Abdallah, Mohammad, Method for performing dual dispatch of blocks and half blocks.
  57. Abdallah, Mohammad, Method for performing dual dispatch of blocks and half blocks.
  58. Glickman, Eran; Ginzburg, Evgeni; Sheffer, Noam, Method for performing plurality of bit operations and a device having plurality of bit operations capabilities.
  59. Abdallah, Mohammad, Method for populating a source view data structure by using register template snapshots.
  60. Abdallah, Mohammad, Method for populating and instruction view data structure by using register template snapshots.
  61. Abdallah, Mohammad, Method for populating register view data structure by using register template snapshots.
  62. Batwara, Ashish; Peterson, James G.; Talagala, Nisha; Zappe, Michael, Methods and appratuses for atomic storage operations.
  63. Abdallah, Mohammad; Rao, Ravishankar; Avudaiyappan, Karthikeyan, Methods, systems and apparatus for predicting the way of a set associative cache.
  64. Abdallah, Mohammad; Rao, Ravishankar; Avudaiyappan, Karthikeyan, Methods, systems and apparatus for predicting the way of a set associative cache.
  65. Abdallah, Mohammad; Rao, Ravishankar; Avudaiyappan, Karthikeyan, Methods, systems and apparatus for predicting the way of a set associative cache.
  66. Abdallah, Mohammad; Groen, Ankur; Gunadi, Erika; Singh, Mandeep; Rao, Ravishankar, Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation.
  67. Erik E. Hagersten ; Christopher J. Jackson ; Aleksandr Guzovskiy ; William A. Nesheim, Multiprocessing computer system employing a cluster communication error reporting mechanism.
  68. Erik E. Hagersten ; Christopher J. Jackson ; Aleksandr Guzovskiy ; William A. Nesheim, Multiprocessing computer system employing a cluster protection mechanism.
  69. Flynn, David, Non-volatile cache.
  70. Kameda, Yasushi; Takeuchi, Ken; Shiga, Hitoshi; Futatsuyama, Takuya; Kawai, Koichi, Non-volatile semiconductor memory device.
  71. Kameda,Yasushi; Takeuchi,Ken; Shiga,Hitoshi; Futatsuyama,Takuya; Kawai,Koichi, Non-volatile semiconductor memory device.
  72. Wilkerson,Christopher B., Parallel processing apparatus, system, and method utilizing correlated data value pairs.
  73. Christopher B. Wilkerson, Parallel processing utilizing highly correlated data values.
  74. Su, Wei-Ming; Chen, Shih Yung, Parallel signal decoding method.
  75. Flynn, David; Nellans, David; Strasser, John; Peterson, James G.; Wipfel, Robert, Preserving data of a volatile memory.
  76. Ashmore, Paul Andrew, Redundant storage controller system with enhanced failure analysis capability.
  77. Abdallah, Mohammad, Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines.
  78. Abdallah, Mohammad, Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines.
  79. Davies, Ian Robert, Safe message transfers on PCI-Express link from RAID controller to receiver-programmable window of partner RAID controller CPU memory.
  80. Erik E. Hagersten, Selective address translation in coherent memory replication.
  81. Hagersten, Erik E., Selective address translation in coherent memory replication.
  82. Evans, Marc Alan; Konas, Pavlos, Set-associative cache memory having variable time decay rewriting algorithm.
  83. Kacevas, Nicolas I., Single array banked branch target buffer.
  84. Kacevas,Nicolas I., Single array banked branch target buffer.
  85. Abdallah, Mohammad, Single cycle multi-branch prediction including shadow cache for early far branch prediction.
  86. Hagersten Erik E. ; Hill Mark D., Skewed finite hashing function.
  87. Chauvel,Gerard; Lasserre,Serge; D'Inverno,Dominique Benoit Jacques, Smart cache.
  88. Marc Tremblay, Software branch prediction filtering for a microprocessor.
  89. Marc Tremblay, Software branch prediction filtering for a microprocessor.
  90. Davies, Ian Robert, System and method for sharing SATA drives in active-active RAID controller system.
  91. Joshi, Vikram; Luan, Yang; Brown, Michael F.; Mehta, Bhavesh; Radhakrishnan, Prashanth, Systems and methods for a de-duplication cache.
  92. Joshi, Vikram; Luan, Yang; Brown, Michael F.; Vidwans, Hrishikesh A., Systems and methods for a file-level cache.
  93. Avudaiyappan, Karthikeyan; Abdallah, Mohammad, Systems and methods for accessing a unified translation lookaside buffer.
  94. Avudaiyappan, Karthikeyan; Abdallah, Mohammad, Systems and methods for accessing a unified translation lookaside buffer.
  95. Talagala, Nisha; Flynn, David; Sundararaman, Swaminathan; Subramanian, Sriram; Nellans, David; Wipfel, Robert; Strasser, John, Systems and methods for atomic storage operations.
  96. Flynn, David; Wipfel, Robert; Nellans, David; Strasser, John, Systems and methods for contextual storage.
  97. Talagala, Nisha; Das, Dhananjoy; Sundararaman, Swaminathan; Batwara, Ashish; Piggin, Nick, Systems and methods for distributed atomic storage operations.
  98. Avudaiyappan, Karthikeyan; Abdallah, Mohammad, Systems and methods for flushing a cache with modified data.
  99. Avudaiyappan, Karthikeyan; Abdallah, Mohammad, Systems and methods for flushing a cache with modified data.
  100. Avudaiyappan, Karthikeyan; Abdallah, Mohammad, Systems and methods for flushing a cache with modified data.
  101. Yang, Jingpei; Talagala, Nisha; Sundararaman, Swaminathan; Plasson, Ned; Gillis, Gregory N., Systems and methods for log coordination.
  102. Avudaiyappan, Karthikeyan; Abdallah, Mohammad, Systems and methods for maintaining the coherency of a store coalescing cache and a load cache.
  103. Avudaiyappan, Karthikeyan; Abdallah, Mohammad, Systems and methods for maintaining the coherency of a store coalescing cache and a load cache.
  104. Joshi, Vikram; Luan, Yang; Apte, Manish R.; Vidwans, Hrishikesh A.; Brown, Michael F., Systems and methods for managing data input/output operations.
  105. Avudaiyappan, Karthikeyan; Abdallah, Mohammad, Systems and methods for non-blocking implementation of cache flush instructions.
  106. Avudaiyappan, Karthikeyan; Abdallah, Mohammad, Systems and methods for non-blocking implementation of cache flush instructions.
  107. Atkisson, David; Nellans, David; Flynn, David; Axboe, Jens; Zappe, Michael, Systems and methods for persistent address space management.
  108. Joshi, Vikram; Luan, Yang; Brown, Michael F.; Mehta, Bhavesh, Systems and methods for persistent cache logging.
  109. Flynn, David; Thatcher, Jonathan; Zappe, Michael, Systems and methods for persistent deallocation.
  110. Flynn, David; Piggin, Nick; Talagala, Nisha, Systems and methods for storage allocation.
  111. Sundararaman, Swaminathan; Talagala, Nisha; Sarto, Eivind; Li, Shaohua, Systems and methods for storage error management.
  112. Avudaiyappan, Karthikeyan; Abdallah, Mohammad, Systems and methods for supporting a plurality of load accesses of a cache in a single cycle.
  113. Avudaiyappan, Karthikeyan; Abdallah, Mohammad, Systems and methods for supporting a plurality of load and store accesses of a cache.
  114. Joshi, Vikram; Luan, Yang; Brown, Michael; Mehta, Bhavesh, Systems, methods and apparatus for a virtual machine cache.
  115. Sundararaman, Swaminathan; Talagala, Nisha; Subramanian, Sriram, Systems, methods and interfaces for data virtualization.
  116. Joshi, Vikram; Luan, Yang; Brown, Michael F.; Flynn, David; Lim Tze Hao, Brent; Zhe Yang, Jerene; Radhakrishnan, Prashanth, Systems, methods, and interfaces for adaptive persistence.
  117. Batwara, Ashish; Peterson, James G.; Talagala, Nisha; Piggin, Nick; Zappe, Michael, Systems, methods, and interfaces for vector input/output operations.
  118. Das, Dhananjoy, Transaction log acceleration.
  119. Petolino, Jr., Joseph A., Translation lookaside buffer (TLB) with reserved areas for specific sources.
  120. Petolino, Jr., Joseph A., Translation lookaside buffer (TLB) with reserved areas for specific sources.
  121. Henry, G. Glenn; McDonald, Thomas C., Variable group associativity branch target address cache delivering multiple target addresses per cache line.
  122. Atkisson, David; Flynn, David, Writing cached data forward on read.
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