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Semiconductor device having a semiconductor chip electrically connected to a wiring substrate 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-013/12
  • H01L-023/48
출원번호 US-0651954 (1996-05-21)
우선권정보 JP-0122026 (1995-05-22)
발명자 / 주소
  • Tsukagoshi Isao,JPX
  • Matsuoka Hiroshi,JPX
  • Hirosawa Yukihisa,JPX
  • Mikami Yoshikatsu,JPX
  • Dokochi Hisashi,JPX
출원인 / 주소
  • Hitachi Chemical Company, Ltd., JPX
대리인 / 주소
    Antonelli, Terry, Stout & Kraus, LLP
인용정보 피인용 횟수 : 63  인용 특허 : 17

초록

A semiconductor device comprising a semiconductor chip, a wiring substrate, and an adhesive preferably containing electroconductive particles interposed therebetween, a plurality of spacer elements being present on or below the adhesive layer, said spacer elements having almost the same height as su

대표청구항

[ What is claimed is:] [1.] A semiconductor device comprising a semiconductor chip electrically connected to a wiring substrate, said chip having a thickness of 0.3 mm or less and a plurality of electrodes on a peripheral portion, the wiring substrate having a plurality of electrodes corresponding t

이 특허에 인용된 특허 (17)

  1. Tago Masamoto (Tokyo JPX) Tanaka Kei (Tokyo JPX), Apparatus for forming a double-bump structure used for flip-chip mounting.
  2. Marrs Robert C. (Scottsdale AZ) Molnar Ronald J. (Phoenix AZ), Ball grid array integrated circuit package with thermal conductor.
  3. Kawakita Tetsuo (Takatsuki JPX) Hatada Kenzo (Katano JPX), Bump electrode for connecting electronic components.
  4. Tanisawa Yasuhisa (Tokyo JPX), Compact optical semiconductor module capable of being readily assembled with a high precision.
  5. Scholz Kenneth D. (4150 Willmar Dr. Palo Alto CA 94306), Compressive bump-and-socket interconnection scheme for integrated circuits.
  6. Laine Eric H. (Binghamton NY) Wilson James W. (Vestal NY), Electronic package.
  7. Lewis Robert L. (Apalachin NY) Sebesta Robert D. (Endicott NY) Waits Daniel M. (Vestal NY), Electronic package with multilevel connections.
  8. Doi Kazuhide (Kawasaki JPX) Miura Masayuki (Kawasaki JPX) Okada Takashi (Kawasaki JPX) Hirano Naohiko (Kawasaki JPX) Hiruta Yoichi (Kashiwa JPX), Flip-chip semiconductor devices having two encapsulants.
  9. Kurogi Garrett I. (Lakewood CA) Swass Matthew J. (El Segundo CA), Hermetically self-sealing flip chip.
  10. Takabayashi Hiroshi (Kawasaki JPX) Takahashi Masanori (Atsugi JPX), Method of mutually connecting electrode terminals.
  11. McBride Donald G. (Binghamton NY) Shaw Jane M. (Ridgefield CT), Organic solder barrier.
  12. Tomoda Yoshiyuki (Tokyo JPX), Plastic-molded semiconductor device containing a semiconductor pellet mounted on a lead frame.
  13. Blanton James A. (Kokomo IN), Provision of substrate pillars to maintain chip standoff.
  14. Kusaka Teruo (Tokyo JPX) Senba Naoji (Tokyo JPX) Nishizawa Atsushi (Tokyo JPX) Takahashi Nobuaki (Tokyo JPX), Sealing structure for bumps on a semiconductor integrated circuit chip.
  15. Kato Takeshi (Kokubunji JPX) Fujita Yuuji (Koganei JPX) Mizuishi Kenichi (Hachioji JPX) Kawata Atumi (Urawa JPX) Itoh Hiroyuki (Akigawa JPX), Semiconductor device having an optical waveguide interposed in the space between electrode members.
  16. Chao Clinton C. (51 Waterside Cir. Redwood City CA 94065) Harper Timothy V. (11260 West Hickory Hill Ct. Boise ID 83704) Wynbeek John C. (10471 Pharlap Dr. Cupertino CA 95014) Schneider Eric S. (3276, Spacing control in electronic device assemblies.
  17. Nishiguchi Masanori (Yokohama JPX) Miki Atsushi (Yokohama JPX), Substrate for packaging a semiconductor device.

이 특허를 인용한 특허 (63)

  1. Hwang, Seong Yong; Oh, Weon Sik; Yoon, Ju Young; Choi, Sung Lak; Song, Chun Ho, Anisotropic conductive film and bump, and packaging structure of semiconductor having the same.
  2. Koji Morita JP, Anisotropically electroconductive adhesive and a ladder filter using the same.
  3. Solo De Zaldivar, Jose; Baumgartner, Peter, Assembly with connecting structure.
  4. Hans-Georg Mensch DE; Stefan Emmert DE; Detlef Houdeau DE, Chip card module.
  5. McCormick, John P., Chip-over-chip integrated circuit package.
  6. Satonaka, Masaharu, Circuit substrate connecting structure, liquid crystal display device having the connecting structure and mounting method of liquid crystal display device.
  7. Yasuhiro Suga JP; Motohide Takeichi JP, Connecting material for anisotropically electroconductive connection.
  8. Itagaki, Masamitsu; Fujihira, Hiroyuki, Connection structure for semiconductor electrode terminals.
  9. Bendix, Lendon L.; Turner, Derek, Control of electric field effects in a printed circuit board assembly using embedded nickel-metal composite materials.
  10. Tongbi Jiang, Electrical circuits, circuits, and electrical couplings.
  11. Noriyuki Honda JP; Yasuhiro Suga JP, Electrical connecting device and electrical connecting method.
  12. Jiang Tongbi, Electrical interconnections.
  13. Jiang, Tongbi, Electrical interconnections, methods of conducting electricity, and methods of reducing horizontal conductivity within an anisotropic conductive adhesive.
  14. Tongbi Jiang, Electrical interconnections, methods of conducting electricity, and methods of reducing horizontal conductivity within an anisotropic conductive adhesive.
  15. Plössl, Andreas; Illek, Stefan, Electrically conducting connection with insulating connection medium.
  16. Matsuhira, Tsutomu; Endo, Atsushi, Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip.
  17. Lehner, Rudolf, Electronic component having a semiconductor chip and method for populating a circuit carrier during the production of the electronic component.
  18. Laine Eric Herman ; Wilson James Warren, Electronic package.
  19. Alcoe, David J.; Calmidi, Varaprasad Venkata; Darbha, Krishna; Sathe, Sanjeev Balwant, Electronic package with thermally conductive standoff.
  20. Nishikawa,Hidenobu; Nishida,Kazuto; Shimizu,Kazumichi; Ono,Shuji; Otani,Hiroyuki, Electronic parts packaging method and electronic parts package.
  21. Wang, Meng-Jen; Chen, Yu-Wen, Face-to-face multi-chip flip-chip package.
  22. Hsuan Min-Chih,TWX ; Lin Cheng-Te,TWX, Face-to-face multi-chip package.
  23. Nakata,Yasukazu; Matsuura,Katsuyoshi; Matsushita,Taiga, Flip chip mounting substrate.
  24. Busick,Steve; Figurelli,Gino, Heated glass panels and methods for making electrical contact with electro-conductive films.
  25. Gaynes, Michael A.; Lewandowski, Eric P.; Nah, Jae-Woong; Polastre, Robert J., Injection of a filler material with homogeneous distribution of anisotropic filler particles through implosion.
  26. Harper, Timothy V.; Allen, Greg L., Integrated circuit package employing flip-chip technology and method of assembly.
  27. Hedler, Harry; Irsigler, Roland; Pohl, Jens, Method for connecting circuit devices.
  28. Ichimura, Takeshi, Method of determining curing conditions, method of producing circuit device, and circuit device.
  29. Chao, Te Tsung; Lii, Mirng Ji; Lin, Chung Yi; Chang, Abel, Method of forming overhang support for a stacked semiconductor device.
  30. Cardot Francis,CHX ; Arquint Philippe,DEX ; van der Schoot Bart,CHX, Micro sensor and method for making same.
  31. Rumer, Christopher L.; Chen, Tian An; Wakharkar, Vijay; Koning, Paul A., No-flow underfill composition and method.
  32. Rumer,Christopher L.; Chen,Tian An; Wakharkar,Vijay; Koning,Paul A., No-flow underfill composition and method.
  33. Chao,Te Tsung; Lii,Mirng Ji; Lin,Chung Yi; Chang,Abel, Overhang support for a stacked semiconductor device, and method of forming thereof.
  34. Ishikawa,Naoki; Baba,Shunji; Kira,Hidehiko; Kobayashi,Hiroshi, RFID tag and method of manufacturing the same.
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  39. Takahashi, Yoshikazu, Semiconductor chip on film package with dummy patterns and manufacturing method thereof.
  40. Suzuki,Takehiro; Toyosawa,Kenji, Semiconductor device.
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  45. Hashimoto, Nobuaki, Semiconductor device and method of manufacture thereof, circuit board and electronic instrument.
  46. Hasimoto,Nobuaki, Semiconductor device and method of manufacture thereof, circuit board and electronic instrument.
  47. Nakayama, Toshiyuki, Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument.
  48. Jaouen Herve,FRX ; Marty Michel,FRX, Semiconductor device having separated exchange means.
  49. Lee, Chun-Yu; Cheng, Ping-Chin, Semiconductor device, a method for making the same, and an LCD monitor comprising the same.
  50. Hashimoto,Nobuaki, Semiconductor device, circuit board and electronic instrument that include an adhesive with conductive particles therein.
  51. Yu, Chen-Hua; Jeng, Shin-Puu; Yeh, Der-Chyang; Chen, Hsien-Wei; Hsieh, Cheng-Chieh; Chiu, Ming-Yen, Semiconductor package for thermal dissipation.
  52. Chang, Jung-Hua; Huang, Cheng-Lin; Lin, Jing-Cheng, Solder bump for ball grid array.
  53. Lin, Jing-Cheng; Yu, Chen-Hua; Lu, Szu-Wei; Lin, Shih Ting; Jeng, Shin-Puu, Solution for reducing poor contact in info packages.
  54. Kazutaka Shibata JP, Structure of semiconductor chip suitable for chip-on-board system and methods of fabricating and mounting the same.
  55. Urasaki Naoyuki,JPX ; Simada Yasusi,JPX ; Tsuru Yoshiyuki,JPX ; Nakaso Akishi,JPX ; Watanabe Itsuo,JPX, Substrate for mounting semiconductor chips.
  56. Yu, Cheemen; Wang, Ken Jian Ming; Chiu, Chin Tien; Liao, Chih Chin; Chen, Han Shiao, Substrate warpage control and continuous electrical enhancement.
  57. Brodsky, Mark A., Texturing of a die pad surface for enhancing bonding strength in the surface attachment.
  58. Roberson, Mark W.; Deane, Philip A.; Williams, Charles Kenneth, Three dimensional multimode and optical coupling devices.
  59. Roberson,Mark W.; Deane,Philip A.; Williams,Charles Kenneth, Three dimensional multimode and optical coupling devices.
  60. Gotoh, Johshi; Okuno, Tatsuya, Underfilling material for semiconductor package.
  61. Gotoh, Johshi; Okuno, Tatsuya, Underfilling material for semiconductor package.
  62. John P. McCormick, Vertically integrated flip chip semiconductor package.
  63. Ho Kai-Kuang,TWX ; Yang Te-Sheng,TWX, Wafer-level chip scale package.
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