$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Ball grid array electronic package standoff design 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/18
  • H05K-003/34
출원번호 US-0601415 (1996-02-14)
발명자 / 주소
  • Hoffman Paul R.
출원인 / 주소
  • Olin Corporation
대리인 / 주소
    Rosenblatt
인용정보 피인용 횟수 : 39  인용 특허 : 24

초록

In alternative embodiments, the standoff contains a flange having a plurality of apertures useful for either mechanically locking an adhesive or for enabling irradiation of an adhesive by a light source. The standoff may contain protrusions for alignment, strength or circuit routing.

대표청구항

[ I claim:] [11.] A ball grid array electronic package, comprising:a base having a central portion and a peripheral portion;a plurality of circuit traces formed on the peripheral portion of said base, each of said circuit traces having an inner end adjacent the central portion of said base and an ex

이 특허에 인용된 특허 (24)

  1. Mahulikar Deepak (Meriden CT) Popplewell James M. (Guilford CT), Aluminum alloy semiconductor packages.
  2. Tanisawa Yasuhisa (Tokyo JPX), Compact optical semiconductor module capable of being readily assembled with a high precision.
  3. Owens Norman L. (Tempe AZ), Compliant standoff for semiconductor packages.
  4. Temple Victor A. K. (Clifton NY) Glascock ; II Homer H. (Millis MA), Hermetic package for a high power semiconductor device.
  5. Jones Tim (Chandler AZ) Ommen Denise (Phoenix AZ) Baird John (Scottsdale AZ), Low-profile ball-grid array semiconductor package.
  6. Mahulikar Deepak (Madison CT) Hoffman Paul R. (Modesto CA) Braden Jeffrey S. (Livermore CA), Metal ball grid array package with improved thermal conductivity.
  7. Pendse Rajendra D. (5245 Diamond Common Fremont CA 94555), Method for making high pin count package for semiconductor device.
  8. Sliwa John W. (Los Altos Hills CA) Burt Roy J. (Sunnyvale CA) Lee Chune (San Francisco CA) MacKay John (Saratoga CA) Johnson Cindy A. (Sunnyvale CA), Method for mounting a semiconductor chip.
  9. Butt Sheldon H. (Godfrey IL), Method of making a hermetically sealed semiconductor casing.
  10. Matsuo Youichi (Tokyo JPX), Package having a heat sink suitable for a ceramic substrate.
  11. Lin Paul T. (Austin TX) Wilson Howard P. (Austin TX), Pad array carrier IC device using flexible tape.
  12. Higgins ; III Leo M. (Austin TX), Pad array semiconductor device having a heat sink with die receiving cavity.
  13. Cohn Charles (Wayne NJ), Plastic pin grid array package.
  14. Tsuji Kazuto (Kawasaki JPX) Hiraoka Tetsuya (Kawasaki JPX) Aoki Tsuyoshi (Sagamihara JPX) Kasai Junichi (Kawasaki JPX), Process of using a jig to align and mount terminal conductors to a semiconductor plastic package.
  15. Blanton James A. (Kokomo IN), Provision of substrate pillars to maintain chip standoff.
  16. Ueda Tetsuya (Itami JPX), Semiconductor device.
  17. Suzuki Katsuhiko (Tokyo JPX), Semiconductor device capable of preventing occurrence of a shearing stress.
  18. Kato Takeshi (Kokubunji JPX) Fujita Yuuji (Koganei JPX) Mizuishi Kenichi (Hachioji JPX) Kawata Atumi (Urawa JPX) Itoh Hiroyuki (Akigawa JPX), Semiconductor device having an optical waveguide interposed in the space between electrode members.
  19. Tsuji Kazuto (Kawasaki JPX) Hiraoka Tetsuya (Kawasaki JPX) Aoki Tsuyoshi (Sagamihara JPX) Kasai Junichi (Kawasaki JPX), Semiconductor device having spherical terminals attached to the lead frame embedded within the package body.
  20. Crane Jacob (Woodbridge CT) Johnson Barry C. (Tucson AZ) Mahulikar Deepak (Meriden CT) Butt Sheldon H. (Godfrey IL), Semiconductor package.
  21. Neidig Arno (Plankstadt DEX), Semiconductor power module with ceramic substrate.
  22. Altendorf John M. (Corvallis OR) Wong Marvin G. (Corvallis OR), Soldering interconnect method for semiconductor packages.
  23. Loo Mike C. (San Jose CA), Tab semiconductor package with cushioned land grid array outer lead bumps.
  24. Lin Paul T. (Austin TX), Three-dimensional multi-chip pad array carrier.

이 특허를 인용한 특허 (39)

  1. Patel Sunil A. ; Chia Chok J. ; Desai Kishor V., Apparatus and method for improving ball joints in semiconductor packages.
  2. Chien-Ping Huang TW; Chien Yuan Tsui TW; Niang Yi Cheng TW, Ball grid array integrated circuit package with palladium coated heat-dissipation device.
  3. Laine Eric Herman ; Wilson James Warren, Electronic package.
  4. Alcoe, David J.; Calmidi, Varaprasad Venkata; Darbha, Krishna; Sathe, Sanjeev Balwant, Electronic package with thermally conductive standoff.
  5. Alcoe, David J.; Calmidi, Varaprasad V., Flexible circuit electronic package with standoffs.
  6. Goetz, Martin P.; Hatcher, Merrill A.; Jones, Christopher E., Hermetic package for surface acoustic wave device having exposed device substrate contacts and method of manufacturing the same.
  7. Saito Yoshio, Hydrogen getter for integrated microelectronic assembly.
  8. Saito, Yoshio, Hydrogen getter for integrated microelectronic assembly.
  9. Yoshio Saito, Hydrogen getter for integrated microelectronic assembly.
  10. Prokofiev,Victor, IC package with power and signal lines on opposing sides.
  11. Bathan, Henry D.; Shim, Il Kwon; Punzalan, Jeffrey D.; Camacho, Zigmund Ramirez, Integrated circuit package system with interconnect support.
  12. Liu, Jwei Wien; O'Connor, John P., Masking layer in substrate cavity.
  13. Liu,Jwei Wien; O'Connor,John P., Masking layer in substrate cavity.
  14. Augustin, Thomas J.; Malon, Christopher G., Method and apparatus for shock and vibration isolation of a circuit component.
  15. Deeney, Jeffrey L., Method and apparatus for supporting a circuit component.
  16. Deeney,Jeffrey L.; Dutson,Joseph D.; Luebs,Richard J., Method and apparatus for supporting a circuit component having solder column interconnects using an external support.
  17. Deeney, Jeffrey L.; Dutson, Joseph D.; Luebs, Richard J., Method and apparatus for supporting a circuit component having solder column interconnects using external support.
  18. Deeney, Jeffrey L., Method and apparatus for supporting circuit component having solder column array interconnects using interposed support shims.
  19. Deeney, Jeffrey L.; Mayer, David W., Method and apparatus of supporting circuit component having a solder column array using interspersed rigid columns.
  20. Augustin,Thomas J.; Malone,Christopher G., Method of a supporting a CGA integrated package on a circuit board with improved shock and vibration isolation.
  21. Howarth, James J., Method of ball grid array (BGA) alignment, method of testing, alignment apparatus and semiconductor device assembly.
  22. Howarth,James J., Method of ball grid array (BGA) alignment, method of testing, alignment apparatus and semiconductor device assembly.
  23. Howarth,James J., Method of semiconductor device package alignment and method of testing.
  24. Goudarzi, Vahid, Method to enhance reliability of through mold via TMVA part on part POP devices.
  25. Komiyama, Tadashi; Hara, Akitoshi; Sato, Eiichi, Methods for manufacturing semiconductor chips, methods for manufacturing semiconductor devices, semiconductor chips, semiconductor devices, connection substrates and electronic devices.
  26. Stapleton, Russell A., Methods for protecting a die surface with photocurable materials.
  27. Stapleton, Russell A., Methods for protecting a die surface with photocurable materials.
  28. Crane, Peter; Polson, Bruce C.; Hipwell, Jr., Roger L., Microactuator assembly having improved standoff configuration.
  29. Downes Stuart, Non-collapsing interconnection for semiconductor devices.
  30. Chun Dong-Seok,KRX, Semiconductor package and method for fabricating same.
  31. Larry D. Kinsman, Semiconductor package having metal foil die mounting plate.
  32. Hoffman, Paul; Mathews, Doug, Shielded semiconductor leadframe package.
  33. Hoffman, Paul; Mathews, Doug, Shielded semiconductor package with single-sided substrate and method for making the same.
  34. Hollinsworth, Jeffrey Lynn; Bicknese, Randy John; Kalra, Varinder Kumar; Spalding, Keith Allen, Surface mount standoff for printed circuit board assembly.
  35. Diao,Qizhong; McLellan,Neil; Kirloskar,Mohan, Thermally enhanced cavity-down integrated circuit package.
  36. Diao,Qizhong; McLellan,Neil; Kirloskar,Mohan, Thermally enhanced cavity-down integrated circuit package.
  37. Distefano Thomas H., Thermally enhanced packaged semiconductor assemblies.
  38. Thomas H. Distefano, Thermally enhanced packaged semiconductor assemblies.
  39. Cherukuri,Kalyan C.; Vigrass,William J., Vertically stacked semiconductor device.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로