초록 ▼

A system for controlling signal transfer between a plurality of devices, for controlling the transfer of signals between a main device having processors packaged therein and a subsidiary device having units packaged therein, includes a multiplexer section on the main device side for multiplexing sig

A system for controlling signal transfer between a plurality of devices, for controlling the transfer of signals between a main device having processors packaged therein and a subsidiary device having units packaged therein, includes a multiplexer section on the main device side for multiplexing signals from a control system processor and a monitor system processor of the main device; a demultiplexer section on a subsidiary side for demultiplexing the multiplex signal from the multiplexer section on the main device side and distributing it to the units of the subsidiary device; a multiplexer section on the subsidiary device side for multiplexing the signals from the units of the subsidiary device; and a demultiplexer section on the main device side for demultiplexing the multiplex signal from the multiplexer section on the subsidiary device side and distributing it to the control system processor and the monitor system processor. The multiplexer section on the main device side executes bit-stuffing and multiplexing in such a manner as to correspond to the phase or frequency difference between clock signals from clock generators and transfers the signal to the subsidiary device through a cable.

대표청구항 ▼

[ We claim:] [1.] A system for controlling signal transfer between a plurality of devices, for controlling the transfer of signals between a main device having at least a control system processor and a monitor system processor packaged therein and a subsidiary device having a plurality of units pack

[ We claim:] [1.] A system for controlling signal transfer between a plurality of devices, for controlling the transfer of signals between a main device having at least a control system processor and a monitor system processor packaged therein and a subsidiary device having a plurality of units packaged therein, including:a multiplexer section on the main device side for multiplexing the signals from said control system processor and said monitor system processor of said main device;a demultiplexer section on the subsidiary device side for demultiplexing a multiplex signal from said multiplexer section on the main device side and distributing it to said units of said subsidiary device;a multiplexer section on the subsidiary side for multiplexing the signal from said units of said subsidiary device; anda demultiplexer section on the main device side for demultiplexing the multiplex signal from said multiplexer section on the subsidiary device side and distributing it to said control system processor and said monitor system processor of said main device, wherein:said multiplexer section on the main device side includes a clock generator for multiplexing, and executes bit-stuffing and multiplexing corresponding to the difference between the phase of a clock signal from said clock generator and the phases of clock signals from clock generators of said control system processor and said monitor system processor, and said demultiplexer section on the subsidiary side includes a phase sync oscillator for generating a clock signal in phase synchronism with the multiplex signal from said multiplexer section on the main side, demultiplexes a multiplex signal multiplexed by bit-stuffing and multiplexing from said multiplexer section on the main device side, by bit-stuffing synchronization, and distributes it to said units.