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Apparatus, system and method for supporting DMA transfers on a multiplexed bus 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0534187 (1995-09-26)
발명자 / 주소
  • Nagaraj Ravi
  • Kunda Aniruddha
  • Akiyama James
출원인 / 주소
  • Intel Corporation
대리인 / 주소
    Blakely, Sokoloff, Taylor & Zafman
인용정보 피인용 횟수 : 98  인용 특허 : 16

초록

An apparatus and method for enabling a Peripheral Component Interconnect ("PCI") bus to support direct memory access ("DMA") transfers. The apparatus comprises a plurality of DMA controllers, a state machine and an internal storage element. The plurality of DMA controllers transfers DMA requests for

대표청구항

[ What is claimed is:] [1.] An apparatus configured to support a direct memory access transfer on a multiplexed bus between a main memory element and an electronic device, the apparatus comprising:a plurality of direct memory access controllers capable of receiving a direct memory access request fro

이 특허에 인용된 특허 (16)

  1. Amini Nader (Boca Raton FL) Bland Patrick M. (Delray Beach FL) Boury Bechara F. (Boca Raton FL) Hofmann Richard G. (Boynton Beach FL) Lohman Terence J. (Boca Raton FL), Arbitration logic for multiple bus computer system.
  2. Bland Patrick M. (Austin TX) Hofmann Richard G. (Cary NC) Katz Sagi (Haifa ILX) Moeller Dennis (Boca Raton FL) Venarchick Lance M. (Boca Raton FL), Bridge between two buses of a computer system that determines the location of memory or accesses from bus masters on one.
  3. Bland Patrick Maurice (Austin TX) Hofmann Richard G. (Cary NC) Moeller Dennis (Boca Raton FL) Venarchick Lance M. (Boca Raton FL), Bridge between two buses of a computer system with a direct memory access controller with accessible registers to suppor.
  4. Bland Patrick M. (Austin TX) Cronin ; III Daniel R. (Lake Worth FL) Hofmann Richard G. (Cary NC) Moeller Dennis (Boca Raton FL) Venarchick Lance M. (Boca Raton FL), Bridge interface between two buses of a computer system with a direct memory access controller programmed by a scatter/g.
  5. Melo Maria L. (Houston TX) Bonella Randy M. (Cypress TX), Bus master arbitration circuitry having improved prioritization.
  6. Kotzur Gary B. (Spring TX), Circuit for ensuring that a local interrupt controller in a microprocessor is powered up active.
  7. Padgett Russell S. (West Palm Beach FL) Nassiff Amado (Hialeah FL) Rauenzahn ; II Spencer G. (Delray Beach FL), Configuration and RAM/ROM control of PCI extension card residing on MCA adapter card.
  8. Metzger Stephen D. (Lancaster MA) Lomicka Jeffrey A. (Maynard MA) Vacon Gary (Melrose MA) Gili Pat (Westfield MA), Disposition filtering of messages using a single address and protocol table bridge.
  9. Gildea Kevin J. (Bloomington NY) Hochschild Peter H. (New York NY) Huang Yun-Pong (Hurley NY), Method and apparatus for managing packet FIFOS.
  10. Ludwig Thomas E. (Irvine CA) Craft Thomas W. (Mission Viejo CA), Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus.
  11. Stambaugh Mark A. (Houston TX) Sacarisen Stephen P. (Houston TX) Patrick Michael W. (Houston TX), Microprocessor device with integrated auto-loaded timer.
  12. Chang Ki S. (Houston TX) Patrick Michael W. (Houston TX) Sacarisen Stephen P. (Houston TX) Stambaugh Mark A. (Houston TX), Microprocessor with integrated CPU, RAM, timer, and bus arbiter for data communications systems.
  13. Stancil Charles J. (Tomball TX) Vaughn William M. (Houston TX) Wolford Jeff W. (Spring TX), Non-conforming PCI bus master timing compensation circuit.
  14. Sy Kian-Bon K. (432 Farmstead Dr. Cary NC 27511), Routing mechanism with encapsulated FCS for a multi-ring local area network.
  15. Amini Nader (Boca Raton FL) Bland Patrick M. (Delray Beach FL) Boury Bechara F. (Boca Raton FL) Hofmann Richard G. (Boynton Beach FL) Lohman Terence J. (Boca Raton FL), System direct memory access (DMA) support logic for PCI based computer system.
  16. Larson John E. (Katy TX) Moriarty Michael (Spring TX) Collins Michael J. (Tomball TX) Thome Gary W. (Tomball TX), System for arbitrating access to memory with dynamic priority assignment.

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