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Radiation-hard, low power, sub-micron CMOS on a SOI substrate 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/84
출원번호 US-0658188 (1996-06-04)
발명자 / 주소
  • Vu Truc Q.
  • Chang Chen-Chi P.
  • Cable James S.
  • Li Mei F.
출원인 / 주소
  • Raytheon Company
대리인 / 주소
    Alkov
인용정보 피인용 횟수 : 43  인용 특허 : 0

초록

A radiation-hard, low-power semiconductor device of the complementary metal-oxide semiconductor (CMOS) type which is fabricated with a sub-micron feature size on a silicon-on-insulator (SOI) substrate (12). The SOI substrate may be of several different types. The sub-micron CMOS SOI device has both

대표청구항

[ What is claimed is:] [1.] A method for fabricating a silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) device which has low power consumption and is radiation-hard, said method comprising steps in sequence of:a) providing an SOI processing wafer having a bulk silicon body,

이 특허를 인용한 특허 (43)

  1. Fazan, Pierre C.; Sandhu, Gurtej S., Apparatus having trench isolation structure with reduced isolation pad height and edge spacer.
  2. Drab, John J.; Teshiba, Mary A., Coaxial connector feed-through for multi-level interconnected semiconductor wafers.
  3. Chen,Young Kai; Houtsma,Vincent Etienne; Weimann,Nils Guenter, Dissipative isolation frames for active microelectronic devices, and methods of making such dissipative isolation frames.
  4. Huang, Chiu-Tsung; Yeh, Wen-Kuan; Liu, Lu-Min, Electrostatic discharge protection apparatus with silicon control rectifier and the method of fabricating the same.
  5. Akram Salman ; Ditali Akram, Field effect transistor having improved hot carrier immunity.
  6. Matthew S. Buynoski, Frontside SOI gettering with phosphorus doping.
  7. Wang, Hongmei; Zahurak, John K., Fully-depleted (FD)(SOI) MOSFET access transistor and method of fabrication.
  8. Chan, Simon Siu-Sing, Inert atom implantation method for SOI gettering.
  9. Fisher, Philip; Lin, Ming-Ren; Buynoski, Matthew S., Linerless shallow trench isolation method.
  10. Xiang, Qi, Low density, tensile stress reducing material for STI trench fill.
  11. Thaper, Narash, Low voltage power MOSFET device and process for its manufacture.
  12. Xiang, Qi; Fisher, Philip A., Method and apparatus for STI using passivation material for trench bottom liner.
  13. Bin Yu ; Che-Hoo Ng, Method and apparatus for suppressing the channeling effect in high energy deep well implantation.
  14. Fazan Pierre C.,CHX ; Sandhu Gurtej S., Method and apparatus for trench isolation process with pad gate and trench edge spacer elimination.
  15. Pierre C. Fazan CH; Gurtej S. Sandhu, Method and apparatus for trench isolation process with pad gate and trench edge spacer elimination.
  16. Pierre C. Fazan CH; Gurtej S. Sandhu, Method and apparatus for trench isolation process with pad gate and trench edge spacer elimination.
  17. Brown, Jeffrey Scott; Bryant, Andres; Gauthier, Jr., Robert J.; Mann, Randy William; Voldman, Steven Howard, Method and structures for dual depth oxygen layers in silicon-on-insulator processes.
  18. Witold P. Maszara ; Ming-Ren Lin ; Qi Xiang, Method for and device having STI using partial etch trench bottom liner.
  19. Summer, Steven E., Method for implementing radiation hardened, power efficient, non isolated low output voltage DC/DC converters with non-radiation hardened components.
  20. Darmawan Johan ; Olgaard Christian ; Lee Tsung Wen, Method for producing semiconductor-on-insulator structure with reduced parasitic capacitance.
  21. Xiang, Qi; Fisher, Philip A., Method for shallow trench isolation using passivation material for trench bottom liner.
  22. Fisher, Philip; Chan, Darin A., Method for shallow trench isolation with removal of strained island edges.
  23. Akram, Salman; Ditali, Akram, Methods of forming a transistor gate.
  24. Akram,Salman; Ditali,Akram, Methods of forming a transistor gate.
  25. Canham, John S., Methods of forming radiation-hardened semiconductor structures.
  26. Yamazaki, Shunpei; Ohtani, Hisashi; Koyama, Jun; Fukunaga, Takeshi, Nonvolatile memory and electronic apparatus.
  27. Fletcher,Christopher Lee; Toth,Andrew G.; Cripe,Jerry R., Pin detector apparatus and method of fabrication.
  28. Alexander Yuri Usenko, Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate.
  29. Bedell, Stephen W.; Hekmatshoartabari, Bahman; Khakifirooz, Ali; Shahidi, Ghavam G.; Shahrjerdi, Davood, Radiation hardened SOI structure and method of making same.
  30. Bedell, Stephen W.; Hekmatshoartabari, Bahman; Khakifirooz, Ali; Shahidi, Ghavam G.; Shahrjerdi, Davood, Radiation hardened SOI structure and method of making same.
  31. Witold P. Maszara, SOI semiconductor device opening implantation gettering method.
  32. Nakamura,Mitsutoshi; Amakawa,Hirotaka, Semiconductor device.
  33. Kuwabara, Hideaki; Tanaka, Koichiro, Semiconductor device and manufacturing method thereof.
  34. Ushiku, Yukihiro, Semiconductor device and method of manufacturing the same.
  35. Yamazaki,Shunpei; Ohtani,Hisashi; Koyama,Jun; Fukunaga,Takeshi, Semiconductor device having SOI structure and manufacturing method thereof.
  36. Koh Yo Hwan,KRX ; Choi Jin Hyeok,KRX, Semiconductor device having a T-shaped field oxide layer and a method for fabricating the same.
  37. Yamazaki, Shunpei; Ohtani, Hisashi; Koyama, Jun; Fukunaga, Takeshi, Semiconductor device having buried oxide film.
  38. Okihara, Masao, Semiconductor device with selected transistor properties.
  39. Kuwabara,Hideaki; Tanaka,Koichiro, Semiconductor manufacturing method.
  40. Akram,Salman; Ditali,Akram, Semiconductor processing method and field effect transistor.
  41. Schwank James R. ; Shaneyfelt Marty R. ; Draper Bruce L. ; Dodd Paul E., Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications.
  42. Wolfe, Jesse D.; Theiss, Steven D.; Carey, Paul G.; Smith, Patrick M.; Wickboldt, Paul, Thin film transistors on plastic substrates with reflective coatings for radiation protection.
  43. Wolfe,Jesse D.; Theiss,Steven D.; Carey,Paul G.; Smith,Patrick M.; Wickboldt,Paul, Thin film transistors on plastic substrates with reflective coatings for radiation protection.
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