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Method for reducing surface leakage current on semiconductor intergrated circuits during polyimide passivation

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01C-021/4762
출원번호 US-0755862 (1996-12-02)
발명자 / 주소
  • Fu Wen-Jui,TWX
  • Lan Ho-Ku,TWX
  • Chao Ying-Chen,TWX
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, Ltd., TWX
대리인 / 주소
    Saile
인용정보 피인용 횟수 : 24  인용 특허 : 0

초록

A method is achieved for reducing the surface leakage current between adjacent bonding pads on integrated circuit substrates after forming a patterned polyimide passivation layer. When the polyimide layer is patterned to open contacts areas over the bonding pads, plasma ashing in oxygen is used to r

대표청구항

[ What is claimed is:] [1.] A method of forming a polyimide passivation layer on semiconductor integrated circuits with reduced surface leakage currents between bonding pads, comprising the steps of;providing a semiconducting substrate having semiconductor devices formed in and on said substrate, sa

이 특허를 인용한 특허 (24)

  1. Wu Jyh-Ren,TWX ; Liu Chia-Chen,TWX, Bonding pad structure and manufacturing method thereof.
  2. Usui, Ryosuke; Mizuhara, Hideki; Igarashi, Yusuke; Sakamoto, Noriaki, Circuit device manufacturing method.
  3. Usui,Ryosuke; Mizuhara,Hideki; Igarashi,Yusuke; Sakamoto,Noriaki, Circuit device manufacturing method.
  4. Usui,Ryosuke; Mizuhara,Hideki; Igarashi,Yusuke; Sakamoto,Noriaki, Circuit device manufacturing method including mounting circuit elements on a conductive foil, forming separation grooves in the foil, and etching the rear of the foil.
  5. Cheu, Shih-Shiung; Sheu, Yea-Dean; Shen, Chih-Heng, Cost effective polymide process to solve passivation extrusion or damage and SOG delminates.
  6. Peng Chiang-Jen,TWX ; Lin Ching-Chung,TWX, Method and apparatus with heat treatment for stripping photoresist to eliminate post-strip photoresist extrusion defects.
  7. Visser, Tymen; Ungerank, Markus; Balster, Jörg; Führer, Christoph, Method for producing polyimide membranes.
  8. Mizuki Segawa JP; Michikazu Matsumoto JP; Masahiro Yasumi JP, Method of fabricating semiconductor device.
  9. Chen Sheng-Hsiung,TWX, Method of improving copper pad adhesion.
  10. Chen,Sheng Hsiung, Method of improving copper pad adhesion.
  11. Yabu Toshiki,JPX ; Segawa Mizuki,JPX, Method of making a semiconductor device.
  12. Nakatani, Goro, Method of manufacturing a semiconductor device having an enhanced electrode pad structure.
  13. Tobimatsu, Hiroshi; Kamiura, Yuuki; Okura, Seiji; Sawada, Mahito, Method of manufacturing semiconductor device having passivation film and buffer coating film.
  14. Chang Tony,TWX ; Cheng Shiang-Peng,TWX, Method of reducing pin holes in a nitride passivation layer.
  15. Fan, Yang-Tung; Chu, Cheng-Yu; Peng, Chiou-Shian; Lin, Shih-Jane; Chen, Yen-Ming; Fan, Fu-Jier; Lin, Kuo-Wei, Method to form a color image sensor cell while protecting the bonding pad structure from damage.
  16. Lin, Mou-Shiung; Lee, Jin-Yuan, Non-cyanide gold electroplating for fine-line gold traces and gold pads.
  17. Wang, Yiqiong; Khan, Anisul; Kumar, Ajay; Podlesnik, Dragan; Pamarthy, Sharma V., Process for etching conductors at high etch rates.
  18. Yabu Toshiki,JPX ; Segawa Mizuki,JPX, Semiconductor interconnect formed over an insulation and having moisture resistant material.
  19. Yabu, Toshiki; Segawa, Mizuki, Semiconductor interconnect formed over an insulation and having moisture resistant material.
  20. Yabu,Toshiki; Segawa,Mizuki, Semiconductor interconnect formed over an insulation and having moisture resistant material.
  21. Krishna Seshan ; M. Lawrence A. Dass ; Geoffrey L. Bakker, Semiconductor passivation deposition process for interfacial adhesion.
  22. Seshan,Krishna; Dass,M. Lawrence A.; Bakker,Geoffrey L., Semiconductor passivation deposition process for interfacial adhesion.
  23. Letz, Tobias; Lehr, Matthias; Hohage, Joerg; Kuechenmeister, Frank, Technique for forming a passivation layer without a terminal metal.
  24. Lee Daniel Hao-Tien,TWX ; Ko Jun-Cheng,TWX, UV resist curing as an indirect means to increase SiN corner selectivity on self-aligned contact etching process.

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