[특허]Methods for fabricating multichip semiconductor structures with consolidated circuitry and programmable ESD protection f

Methods for fabricating multichip semiconductor structures with consolidated circuitry and programmable ESD protection f 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G11C-005/06
출원번호	US-0785032 (1997-01-02)
발명자 / 주소	Bertin Claude Louis Hedberg Erik Leigh Leas James Marc Voldman Steven Howard
출원인 / 주소	International Business Machines Corporation
대리인 / 주소	Heslin & Rothenberg, P.C.
인용정보	피인용 횟수 : 79 인용 특허 : 0

초록 ▼

Multichip semiconductor structures with consolidated circuitry are disclosed, along with programmable electrostatic discharge (ESD) protection circuits for chip input/output (I/O) nodes. The multichip structures include a first semiconductor chip having a first circuit at least partially providing a first predetermined circuit function, and a second semiconductor chip electrically and mechanically coupled to the first semiconductor chip. The second semiconductor device chip has a second circuit that at least partially provides a circuit function to the first circuit of the first semiconductor chip. In one embodiment, the first semiconductor chip comprises a memory array chip, while the second semiconductor chip comprises a logic chip wherein at least some peripheral circuitry necessary for accessing the memory array of the memory array chip resides within the logic chip. This allows the removal of redundant circuitry from identical chips of a multichip structure. Also disclosed is removing, adding or balancing ESD circuit loading on input/output nodes of a multichip stack. Various techniques are presented for selective removal of ESD circuitry from commonly connected I/O nodes. Any circuitry interfacing with an external device may be rebalanced at the multichip level using this concept.

대표청구항 ▼

[ We claim:] [1.] A method for fabricating a multichip semiconductor stack having input/output (I/O) nodes with customizable electrostatic discharge protection, said method comprising the steps of:(a) providing a plurality of semiconductor device chips, each semiconductor device chip comprising an integrated circuit connected to an I/O node and an electrostatic discharge suppression circuit designed to have an electrical connection to said I/O node;(b) laminating said plurality of integrated circuit chips such that a planar main surface of each semiconductor device chip is parallel and structurally coupled to a planar main surface of an adjacent semiconductor device chip of said plurality of semiconductor device chips, thereby defining a multichip stack having a side surface;(c) establishing a conductive pattern on said side surface of said multichip stack, said conductive pattern electrically connecting to each of the I/O nodes from the plurality of semiconductor device chips, at least some of said I/O nodes being electrically connected by said conductive pattern as a common I/O node; and(d) disrupting the electrical connection of at least one of said electrostatic discharge suppression circuits to a respective I/O node comprising part of said common I/O node.

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

Methods for fabricating multichip semiconductor structures with consolidated circuitry and programmable ESD protection f 원문보기

초록 ▼

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연합인증

Methods for fabricating multichip semiconductor structures with consolidated circuitry and programmable ESD protection f 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

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이 특허를 인용한 특허 (79)

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