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Field programmable gate array with high speed SRAM based configurable function block configurable as high performance l 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/00
출원번호 US-0790271 (1997-01-28)
발명자 / 주소
  • Steele Randy Charles
  • Chinnow
  • Jr. Duane H.
출원인 / 주소
  • Altera Corporation
대리인 / 주소
    Townsend and Townsend and Crew LLP
인용정보 피인용 횟수 : 96  인용 특허 : 0

초록 ▼

A field programmable gate array (FPGA) includes a number of configurable function blocks, each separately configurable by the user of the FPGA as either high performance programmable logic or a block of SRAM. In accordance with the present invention, each configurable function block includes a volat

대표청구항 ▼

[ We claim:] [1.] A configurable function block comprising:input means for inputting input signals to said configurable function block;output means for outputting output signals from said configurable function block;means for operating said configurable function block as programmable logic to perfor

이 특허를 인용한 특허 (96)

  1. Pedersen Bruce, Apparatus and method for centralized generation of an enabled clock signal for a logic array block of a programmable logic device.
    상세보기
  2. Kuo,Wei Min; Yu,Donald Y., Apparatus for interfacing and testing a phase locked loop in a field programmable gate array.
    상세보기
  3. Kuo, Wei-Min; Yu, Donald Y., Apparatus for testing a phrase-locked loop in a boundary scan enabled device.
    상세보기
  4. Swami,Parvesh; Khanna,Namerita; Agarwal,Deepak, Architecture for programmable logic device.
    상세보기
  5. Bots, Henk J.; Hunt, William E.; Palma, Derek; Lawler, John, Architecture for virtual private networks.
    상세보기
  6. Bots,Henk J.; Hunt,William E.; Palma,Derek; Lawler,John, Architecture for virtual private networks.
    상세보기
  7. Kundu, Arunangshu; Fron, Jerome, Carry chain for use between logic modules in a field programmable gate array.
    상세보기
  8. Kundu, Arunangshu, Clock tree network in a field programmable gate array.
    상세보기
  9. Kundu, Arunangshu, Clock tree network in a field programmable gate array.
    상세보기
  10. Kundu,Arunangshu, Clock tree network in a field programmable gate array.
    상세보기
  11. Andy L. Lee ; Christopher F. Lane ; Srinivas T. Reddy ; Brian D. Johnson ; Ketan H. Zaveri ; Mario Guzman ; Quyen Doan, Configurable memory structures in a programmable logic device.
    상세보기
  12. Francis B. Heile, Content addressable memory encoded outputs.
    상세보기
  13. Plants, William C.; Kundu, Arunangshu, Dedicated input/output first in/first out module for a field programmable gate array.
    상세보기
  14. Plants, William C.; Kundu, Arunangshu, Dedicated input/output first in/first out module for a field programmable gate array.
    상세보기
  15. Plants,William C.; Kundu,Arunangshu, Dedicated input/output first in/first out module for a field programmable gate array.
    상세보기
  16. Plants,William C.; Kundu,Arunangshu, Dedicated input/output first in/first out module for a field programmable gate array.
    상세보기
  17. Osann, Jr., Robert; Hallinan, Patrick; Lee, Jung; Mukund, Shridhar, Depopulated programmable logic array.
    상세보기
  18. Osann, Jr.,Robert; Hallinan,Patrick; Lee,Jung; Mukund,Shridhar, Depopulated programmable logic array.
    상세보기
  19. Veenstra Kerry S., Embedded memory block with FIFO mode for programmable logic device.
    상세보기
  20. Veenstra Kerry S., Embedded memory block with FIFO mode for programmable logic device.
    상세보기
  21. Ngai, Tony; Shumarayev, Sergey; Huang, Wei-Jen; Patel, Rakesh; Lai, Tin, Embedded memory blocks for programmable logic.
    상세보기
  22. Tony Ngai ; Sergey Shumarayev ; Wei-Jen Huang ; Rakesh Patel ; Tin Lai, Embedded memory blocks for programmable logic.
    상세보기
  23. Plants William C. ; Joseph James Dean ; Bell Antony G., Embedded static random access memory for field programmable gate array.
    상세보기
  24. Plants, William C., Field programmable gate array architecture including a buffer module and a method of distributing buffer modules in a field programmable gate array.
    상세보기
  25. Yu, Donald Y.; Kuo, Wei Min, Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers.
    상세보기
  26. Yu, Donald Y.; Kuo, Wei-Min, Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers.
    상세보기
  27. Yu,Donald Y.; Kuo,Wei Min, Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers.
    상세보기
  28. Yu,Donald Y.; Kuo,Wei Min, Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers.
    상세보기
  29. Lien Jung-Cheun ; Huang Eddy Chieh ; Sun Chung-yuan ; Feng Sheng, Final design method of a programmable logic device that is based on an initial design that consists of a partial underlying physical template.
    상세보기
  30. Xiao Ping ; Yin YiYian P., High density PLD structure with flexible logic built-in blocks.
    상세보기
  31. Chang Wanli ; Jefferson David, High speed programmable address decoder.
    상세보기
  32. Wanli Chang ; David Jefferson, High speed programmable address decoder.
    상세보기
  33. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H., I/O buffer circuit with pin multiplexing.
    상세보기
  34. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H., I/O buffer circuit with pin multiplexing.
    상세보기
  35. Osann, Jr.,Robert; Eltoukhy,Shafy; Mukund,Shridhar; Smith,Lyle, Implementing programmable logic array embedded in mask-programmed ASIC.
    상세보기
  36. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H., Input/output buffer with overcurrent protection circuit.
    상세보기
  37. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H., Input/output buffer with overcurrent protection circuit.
    상세보기
  38. Lien Jung-Cheun ; Feng Sheng ; Sun Chung-yuan ; Huang Eddy Chieh, Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure.
    상세보기
  39. Chan, Richard, Method and apparatus for a flexible chargepump scheme for field-programmable gate arrays.
    상세보기
  40. McCollum, John, Method and apparatus for bootstrapping a programmable antifuse circuit.
    상세보기
  41. Jung-Cheun Lien ; Sheng Feng ; Chung-yuan Sun ; Eddy Chieh Huang, Method and apparatus for storing a validation number in a field-programmable gate array.
    상세보기
  42. Sun, Chung; Huang, Eddy C., Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array.
    상세보기
  43. Sun,Chung; Huang,Eddy C., Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array.
    상세보기
  44. Sun,Chung; Huang,Eddy C., Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array.
    상세보기
  45. Kundu, Arunangshu; Narayanan, Venkatesh; McCollum, John; Plants, William C., Multi-level routing architecture in a field programmable gate array having transmitters and receivers.
    상세보기
  46. Kundu,Arunangshu; Narayanan,Venkatesh; McCollum,John; Plants,William C., Multi-level routing architecture in a field programmable gate array having transmitters and receivers.
    상세보기
  47. Reddy, Srinivas; Jefferson, David; Lane, Christopher F.; Santurkar, Vikram; Cliff, Richard, Multiple size memories in a programmable logic device.
    상세보기
  48. Venkata,Ramanand; Lee,Chong H; Patel,Rakesh, Multiple transmit data rates in programmable logic device serial interface.
    상세보기
  49. Sun, Shin Nan; Wong, Wayne W., Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA.
    상세보기
  50. Sun, Shin-Nan; Wong, Wayne W., Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA.
    상세보기
  51. Sun,Shin Nan; Wong,Wayne W., Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA.
    상세보기
  52. Furuta Koichiro,JPX ; Fujii Taro,JPX ; Motomura Masato,JPX, Programmable device with an array of programmable cells and interconnection network.
    상세보기
  53. Veenstra Kerry ; Heile Francis B., Programmable logic architecture incorporating a content addressable embedded array block.
    상세보기
  54. Veenstra Kerry ; Heile Francis B., Programmable logic architecture incorporating a content addressable embedded array block.
    상세보기
  55. Francis B. Heile, Programmable logic array device with random access memory configurable as product terms.
    상세보기
  56. Heile Francis B., Programmable logic array device with random access memory configurable as product terms.
    상세보기
  57. Heile Francis B., Programmable logic array device with random access memory configurable as product terms.
    상세보기
  58. Heile, Francis B., Programmable logic array device with random access memory configurable as product terms.
    상세보기
  59. Osann, Jr., Robert; Eltoukhy, Shafy; Mukund, Shridhar; Smith, Lyle, Programmable logic array embedded in mask-programmed ASIC.
    상세보기
  60. Osann, Jr., Robert; Eltoukhy, Shafy; Mukund, Shridhar; Smith, Lyle, Programmable logic array embedded in mask-programmed ASIC.
    상세보기
  61. Lytle Craig S. ; Faria Donald F., Programmable logic array integrated circuit incorporating a first-in first-out memory.
    상세보기
  62. Lytle Craig S. ; Faria Donald F., Programmable logic array integrated circuit incorporating a first-in first-out memory.
    상세보기
  63. Craig S. Lytle ; Donald F. Faria, Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory.
    상세보기
  64. Lytle Craig S. ; Faria Donald F., Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory.
    상세보기
  65. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.
    상세보기
  66. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.
    상세보기
  67. Cliff Richard G. ; Cope L. Todd ; McClintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.
    상세보기
  68. Cliff Richard G. ; Cope L. Todd ; McClintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.
    상세보기
  69. Cliff, Richard G.; Ahanin, Bahram; Lytle, Craig Schilling; Heile, Francis B.; Pedersen, Bruce B.; Veenstra, Kerry, Programmable logic array integrated circuits.
    상세보기
  70. Cliff, Richard G.; Cope, L. Todd; Mc Clintock, Cameron R.; Leong, William; Watson, James A.; Huang, Joseph; Ahanin, Bahram, Programmable logic array integrated circuits.
    상세보기
  71. Sasaki Paul T., Programmable logic device.
    상세보기
  72. Tony K. Ngai ; Rakesh H. Patel ; Srinivas T. Reddy ; Richard G. Cliff, Programmable logic device having embedded dual-port random access memory configurable as single-port memory.
    상세보기
  73. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H. ; Chen Chao Chiang, Programmable logic device with multi-port memory.
    상세보기
  74. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H. ; Chen Chao Chiang, Programmable logic device with multi-port memory.
    상세보기
  75. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H. ; Chen Chao Chiang, Programmable logic device with multi-port memory.
    상세보기
  76. Sample Stephen P. ; Butts Michael R. ; Norman Kevin A. ; Patel Rakesh H. ; Chen Chao Chiang, Programmable logic device with multi-port memory.
    상세보기
  77. Francis B. Heile, Programmable logic devices with improved content addressable memory capabilities.
    상세보기
  78. Heile Francis B., Programmable logic devices with improved content addressable memory capabilities.
    상세보기
  79. Mendel David W., Programmable logic integrated circuit architecture incorporating a lonely register.
    상세보기
  80. Mendel David W., Programmable logic integrated circuit architecture incorporating a lonely register.
    상세보기
  81. Kundu, Arunangshu; Sather, Eric; Plants, William C., Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks.
    상세보기
  82. Kundu, Arunangshu; Sather, Eric; Plants, William C., Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks.
    상세보기
  83. Kundu,Arunangshu; Sather,Eric; Plants,William C., Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks.
    상세보기
  84. Plants William C., SRAM bus architecture and interconnect to an FPGA.
    상세보기
  85. Plants, William C., SRAM bus architecture and interconnect to an FPGA.
    상세보기
  86. Plants,William C., SRAM bus architecture and interconnect to an FPGA.
    상세보기
  87. Elftmann, Daniel; Speers, Theodore; Kundu, Arunangshu, Synchronous first-in/first-out block memory for a field programmable gate array.
    상세보기
  88. Elftmann,Daniel; Speers,Theodore; Kundu,Arunangshu, Synchronous first-in/first-out block memory for a field programmable gate array.
    상세보기
  89. Elftmann,Daniel; Speers,Theodore; Kundu,Arunangshu, Synchronous first-in/first-out block memory for a field programmable gate array.
    상세보기
  90. Feng, Sheng; Lien, Jung-Cheun; Huang, Eddy C.; Sun, Chung-Yuan; Liu, Tong; Liao, Naihui; Xiong, Weidong, Tileable field-programmable gate array architecture.
    상세보기
  91. Feng,Sheng; Lien,Jung Cheun; Huang,Eddy C.; Sun,Chung Yuan; Liu,Tong; Liao,Naihui; Xiong,Weidong, Tileable field-programmable gate array architecture.
    상세보기
  92. Feng,Sheng; Lien,Jung Cheun; Huang,Eddy C.; Sun,Chung Yuan; Liu,Tong; Liao,Naihui; Xiong,Weidong, Tileable field-programmable gate array architecture.
    상세보기
  93. Feng,Sheng; Lien,Jung Cheun; Huang,Eddy C.; Sun,Chung Yuan; Liu,Tong; Liao,Naihui; Xiong,Weidong, Tileable field-programmable gate array architecture.
    상세보기
  94. Lien, Jung-Cheun; Feng, Sheng; Huang, Eddy C.; Sun, Chung-Yuan; Liu, Tong; Liao, Naihui, Tileable field-programmable gate array architecture.
    상세보기
  95. Pedersen,Bruce B, Versatile RAM for a programmable logic device.
    상세보기
  96. Pedersen,Bruce B, Versatile RAM for programmable logic device.
    상세보기

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