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Advanced modular cell placement system with neighborhood system driven optimization

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/00
출원번호 US-0674605 (1996-06-28)
발명자 / 주소
  • Scepanovic Ranko
  • Koford James S.
  • Andreev Alexander E.,RUX
출원인 / 주소
  • LSI Logic Corporation
대리인 / 주소
    Mitchell, Silberberg & Knupp LLP
인용정보 피인용 횟수 : 6  인용 특허 : 76

초록

A system for computing an affinity for relocating a cell on a surface of a semiconductor chip is disclosed herein. The cell is located within a region and belongs to a net of cells. The system initially computes a weight associated with all cells in the net. The sytem then sums the weights of all ce

대표청구항

[ We claim:] [1.] A method for optimizing the placement of cells on the surface of an integrated circuit device, said method comprising:(a) Supplying a netlist, said netlist comprising cells and nets connected in a predetermined manner so as to define an integrated circuit;(b) forming a cluster of c

이 특허에 인용된 특허 (76)

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  41. Hattori Toshihiro (Kokubunji JPX) Miura Chihei (Kodaira JPX) Miyamoto Shunsuke (Tokyo JPX), Method and system for layout design of integrated circuits with a data transferring flow.
  42. Kim Michelle Y. (Scarsdale NY), Method and system for providing a non-rectangular floor plan.
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  55. Catlin Gary M. (Cupertino CA), Multiple processor accelerator for logic simulation.
  56. Lee Tsu-Chang (San Jose CA), Multiple-layer contour searching method and apparatus for circuit building block placement.
  57. Koza John R. (25372 La Rena La. Los Altos Hills CA 94022), Non-linear genetic algorithms for solving problems by finding a fit composition of functions.
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  73. Burns Richard J. (Canyon Country CA) Mehranfar Stacy W. (Thousand Oaks CA), Technology independent integrated circuit mask artwork generator.
  74. Frankle Jon A. (San Jose CA) Chene Mon-Ren (Cupertino CA), Timing driven method for laying out a user\s circuit onto a programmable integrated circuit device.
  75. Agrawal Bhuwan (Chapel Hill NC) Bello Stephen E. (Kingston NY) Donath Wilm E. (Pleasantville NY) Han San Y. (Poughkeepsie NY) Hutt ; Jr. Joseph (Poughkeepsie NY) Kurtzberg Jerome M. (Yorktown Heights, Timing driven placement.
  76. Hiwatashi Tamotsu (Yokohama JPX), Wiring method for semiconductor integrated circuit.

이 특허를 인용한 특허 (6)

  1. Narendra V. Shenoy ; Hi-Keung Ma ; Mahesh A. Iyer ; Robert F. Damiano ; Kevin M. Harer, Adaptive cell separation and circuit changes driven by maximum capacitance rules.
  2. Stenz, Guenter, Analytical placement methods with minimum preplaced components.
  3. Demirci, Oguz; Paniconi, Marco, Dynamic clustering for adaptive prediction filters.
  4. Kikuchi Hideo,JPX, Figure layout compaction method and compaction device.
  5. Sherlekar Deepak D. ; Selinger Craig R., Method and system for removing hardware design overlap.
  6. Ricky D. Hangartner, Probabilistic computing methods and apparatus.
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