이 특허를 인용한 특허 (73)

1. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.

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2. Paver, Nigel C.; Khan, Moinul H.; Aldrich, Bradley C., Add-subtract coprocessor instruction execution on complex number components with saturation and conditioned on main processor condition flags.

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3. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.

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4. Chang, Nai-Shung; Chen, Tsai-Sheng; Chen, Shu-Hui, Chipset supporting multiple CPU's and layout method thereof.

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5. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.

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6. Tanaka, Sadahiro; Wadsworth, Robert D.; Uchida, Yoshiki; Lin, Denny M.; Tanahashi, Junichi, Compiler that decrypts encrypted source code.

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7. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.

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8. Khan,Moinul H.; Paver,Nigel C.; Aldrich,Bradley C., Cross multiply and add instruction and multiply and subtract instruction SIMD execution on real and imaginary components of a plurality of complex data elements.

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9. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

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10. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

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11. Vorbach, Martin; Thomas, Alexander, Data processing device and method.

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12. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.

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13. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.

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14. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.

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15. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.

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16. Kulp,James; Bardouleau,Graham P.; Gallerie,Ronald J.; Laundree,John E.; Brauner,Raul E., Digital data processing apparatus and methods with dynamically configurable application execution on accelerated resources.

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17. Paver,Nigel C.; Yu,Wing K.; Ganeshan,Murli, Extracting aligned data from two source registers without shifting by executing coprocessor instruction with mode bit for deriving offset from immediate or register.

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18. Miller, Mark Lee; Priddy, Michael Scott, Finite state automata security system.

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19. Miller, Mark Lee; Priddy, Michael Scott, Finite state automation for emulation of activity sequenced engine.

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20. Kulp,James; Bardouleau,Graham P.; Gallerie,Ronald J.; Laundree,John E.; Brauner,Raul E., Framework and methods for dynamic execution of digital data processor resources.

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21. Makowski, Thomas A.; Schmit, Geoffrey, Graphical program node for generating a measurement program.

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22. Mark Lee Miller ; Michael Scott Priddy, Graphical programming environment for deterministic finite state automata.

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23. Hellestrand Graham R. ; Chan Ricky L. K.,AUX ; Kam Ming Chi,AUX ; Torossian James R.,AUX, Hardware and software co-simulation including executing an analyzed user program.

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24. Hellestrand, Graham R.; Chan, Ricky L. K.; Kam, Ming Chi; Torossian, James R., Hardware and software co-simulation including executing an analyzed user program.

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25. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.

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26. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.

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27. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.

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28. Shui, Yaxin; Terry, Phil; Robertson, Kevin; Hong, Quang; Vuong, Bao K., Interface device for interfacing a main processor to processing engines and classifier engines, and methods for configuring and operating interface devices.

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29. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

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30. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.

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31. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.

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32. Colavin, Osvaldo; Rizzo, Davide, Method and apparatus to adapt the clock rate of a programmable coprocessor for optimal performance and power dissipation.

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33. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.

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34. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.

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35. Ripa, Alberto Alessandro Della; Benschop, Peter; Clovis, Philip Michael; Bouvier, Peter Mark; Michel, Steven Dean; Dvorman, David; Escobar, Diego, Method for automatically generating code to define a system of hardware elements.

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36. Vorbach, Martin, Method for debugging reconfigurable architectures.

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37. Vorbach, Martin, Method for debugging reconfigurable architectures.

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38. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.

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39. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.

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40. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.

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41. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.

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42. Cary Ussery ; Oz Levia ; Raymond Ryan, Method of generating application specific integrated circuits using a programmable hardware architecture.

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43. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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44. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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45. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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46. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.

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47. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

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48. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

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49. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.

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50. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.

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51. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.

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52. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.

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53. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).

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54. Paver,Nigel C.; Aldrich,Bradley C., Processing for associated data size saturation flag history stored in SIMD coprocessor register using mask and test values.

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55. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.

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56. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.

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57. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.

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58. Kuesel, Jamie R.; Kupferschmidt, Mark G.; Schardt, Paul E.; Shearer, Robert A., Providing performance tuned versions of compiled code to a CPU in a system of heterogeneous cores.

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59. Kuesel, Jamie R.; Kupferschmidt, Mark G.; Schardt, Paul E.; Shearer, Robert A., Providing performance tuned versions of compiled code to a CPU in a system of heterogeneous cores.

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60. Vorbach, Martin, Reconfigurable elements.

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61. Vorbach, Martin, Reconfigurable elements.

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62. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.

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63. Vorbach, Martin, Reconfigurable sequencer structure.

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64. Vorbach, Martin, Reconfigurable sequencer structure.

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65. Vorbach, Martin, Reconfigurable sequencer structure.

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66. Vorbach, Martin, Reconfigurable sequencer structure.

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67. Vorbach, Martin; Bretz, Daniel, Router.

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68. Paver, Nigel C.; Aldrich, Bradley C., SIMD processor performing fractional multiply operation with saturation history data processing to generate condition code flags.

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69. Metzgen, Paul, Software-to-hardware compiler with symbol set inference analysis.

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70. Paver,Nigel C.; Aldrich,Bradley C., Storing and transferring SIMD saturation history flags and data size.

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71. Yun, Kenneth Yi; James, Kevin Warren, System and method for reevaluating granted arbitrated bids.

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72. Ofer,Meged, Universal hardware device and method and tools for use therewith.

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73. Vahid,Frank; Lysecky,Roman Lev; Stitt,Gregory Michael, Warp processor for dynamic hardware/software partitioning.

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