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System and method for simulating signal flow through a logic block pattern of a real time process control system 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-094/55
출원번호 US-0725005 (1996-10-01)
발명자 / 주소
  • Leibold William Steven
출원인 / 주소
  • Honeywell Inc.
대리인 / 주소
    Hitt
인용정보 피인용 횟수 : 64  인용 특허 : 8

초록 ▼

A testing system for, and method of, simulating signal flow through a logic block pattern of a real time process control system. The system includes: (1) a memory that contains a data base of input data associated with simulated sensors and a rule base containing control rules and constituting a log

대표청구항 ▼

[ What is claimed is:] [1.] A testing system for simulating signal flow through a logic block pattern of a real time process control system, comprising:a memory that contains a data base of input data associated with simulated sensors and a rule base containing real time control rules and constituti

이 특허에 인용된 특허 (8)

  1. Suzuki Kenichiro (Hirakata JPX) Ohnishi Katsutoshi (Osaka JPX) Sajima Kenji (Amagasaki JPX) Miyata Masanobu (Neyagawa JPX), Apparatus for supporting the development of sequence software to be used in automated equipments, and method thereof.
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  2. Smithline Edward T. (Port Washington NY), Automatically converting structured analysis tool database outputs into an integrated simulation model via transportable.
    상세보기
  3. Lavallee Ronald (Hudson NH) Peacock Thomas C. (Windham NH), Continuous flow chart, improved data format and debugging system for programming and operation of machines.
    상세보기
  4. Asano Shigehiro (Kanagawa-ken JPX) Isobe Shouzou (Kanagawa-ken JPX) Amemiya Jiro (Kanagawa-ken JPX) Muratani Hirofumi (Kanagawa-ken JPX), High speed logic simulation system using time division emulation suitable for large scale logic circuits.
    상세보기
  5. Dangelo Carlos (Los Gatos CA) Watkins Daniel (Los Altos CA) Mintz Doron (Sunnyvale CA), Method and system for creating and validating low level description of electronic design from higher level, behavior-ori.
    상세보기
  6. Kelem Steven H. (Los Altos Hills CA) Knapp Steven K. (Santa Clara CA), Method and system for propagating data type for circuit design from a high level block diagram.
    상세보기
  7. Seidel Jorge P. (San Jose CA) Knapp Steven K. (Santa Clara CA), Method for optimizing resource allocation starting from a high level.
    상세보기
  8. Aono Toshihiro (Ibaraki JPX) Kamejima Kohji (Ibaraki JPX) Hamada Tomoyuki (Abiko JPX), Remote control apparatus and control method thereof.
    상세보기

이 특허를 인용한 특허 (64)

  1. Rowe, Stephen C., Aggregated audio/video crossbar connections.
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  2. Cote, Pierre E, Automation system and method of manufacturing product using automated equipment.
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  3. Singh, Raka, Block-based signal processing.
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  4. Roe, Steve; Nemecek, Craig, Breakpoint control in an in-circuit emulation system.
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  5. Wright, David G.; Williams, Timothy J., Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes.
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  6. Freimark,Ronald J., Computer apparatus for interconnecting an industry standard computer to a proprietary backplane and its associated peripherals.
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  7. Best, Andrew; Ogami, Kenneth; Zhaksilikov, Marat, Configuration of programmable IC design elements.
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  8. Best, Andrew; Ogami, Kenneth; Zhaksilikov, Marat, Configuration of programmable IC design elements.
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  9. Willaeys, Didieb; Asse, Abdallah, Device and method for a system analysis and diagnosis.
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  10. Nemecek, Craig; Roe, Steve, External interface for event architecture.
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  11. Gilbert, Stephen; Beoughter, Ken J.; Lucas, John Michael; Hao, Tennyson; Nixon, Mark J., Graphic element with multiple visualizations in a process environment.
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  12. Anderson, Doug, Graphical user interface with user-selectable list-box.
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  13. Lucas, John Michael; Nixon, Mark J.; Zhou, Ling; Enver, Alper T.; Webb, Arthur, Graphics integration into a process configuration and control environment.
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  14. Nemecek, Craig; Roe, Steve, In-circuit emulator and pod synchronized boot.
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  15. Seguine, Dennis R., Input/output multiplexer bus.
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  16. Sequine, Dennis R., Input/output multiplexer bus.
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  17. Eryurek, Evren; Krouth, Terrance F.; Lansing, Jane E., Integrated configuration system for use in a process plant.
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  18. Nixon,Mark; Blevins,Terrence L.; Wojsznis,Wilhelm K., Integrated distributed process control system functionality on a single computer.
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  19. Blevins,Terrence; Nixon,Mark; Lucas,Michael; Webb,Arthur; Beoughter,Ken, Integration of graphic display elements, process modules and control modules in process plants.
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  20. Nixon, Mark J.; Hao, Tennyson; De Guzman, Francis; Rodriguez, Richard; Valderama, Ryan; Lucas, J. Michael; Beoughter, Ken J.; Gilbert, Stephen, Markup language-based, dynamic process graphics in a process plant user interface.
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  21. Brummel, Hans-Gerd; Düll, Siegmund; Singh, Jatinder P.; Sterzing, Volkmar; Udluft, Steffen, Method for the computerized control and/or regulation of a technical system.
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  22. Law, Gary Keith; Sherriff, Godfrey R.; Nixon, Mark, Methods and apparatus to manage testing of a process control system.
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  23. Hammack, Stephen Gerard; Campney, Bruce Hurbert; Zhou, Ling, Methods for a data driven interface based on relationships between process control tags.
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  24. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
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  25. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
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  26. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
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  27. Snyder, Warren, Microcontroller programmable system on a chip with programmable interconnect.
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  28. Snyder, Warren S, Microcontroller programmable system on a chip with programmable interconnect.
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  29. Blevins, Terrence L.; Wojsznis, Wilhelm K.; Nixon, Mark J.; Wojsznis, Peter, Multi-objective predictive process optimization with concurrent process simulation.
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  30. Kutz, Harold, Numerical band gap.
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  31. Snyder, Warren S.; Mar, Monte, PSOC architecture.
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  32. Snyder, Warren; Mar, Monte, PSOC architecture.
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  33. Snyder, Warren S.; Mar, Monte, PSoC architecture.
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  34. Snyder, Warren S.; Mar, Monte, PSoC architecture.
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  35. Anderson,Douglas H.; Seguine,Dennis, Pinout views for allowed connections in GUI.
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  36. Ogami, Kenneth Y., Power management architecture, method and configuration system.
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  37. Blevins, Terrence Lynn; Nixon, Mark J.; McMillan, Gregory K., Process plant monitoring based on multivariate statistical analysis and on-line process simulation.
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  38. Blevins, Terrence L.; Beoughter, Ken J.; Lucas, J. Michael; Nixon, Mark J., Process plant user interface system having customized process graphic display layers in an integrated environment.
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  39. Hansen, Kai, Process simulation in a computer based control system.
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  40. Snyder, Warren; Mar, Monte, Programmable microcontroller architecture(mixed analog/digital).
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  41. Thiagarajan, Eashwar; Sivadasan, Mohandas Palatholmana; Rohilla, Gajender; Kutz, Harold; Mar, Monte, Programmable sigma-delta analog-to-digital converter.
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  42. Hammack, Stephen G.; Campney, Bruce H.; Gilbert, Stephen C.; Sanchez, Adrian A., Scaling composite shapes for a graphical human-machine interface.
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  43. Hammack, Stephen G.; Campney, Bruce H.; Gilbert, Stephen C.; Sanchez, Adrian A., Scaling composite shapes for a graphical human-machine interface.
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  44. Schleiss, Duncan; Ramachandran, Ram; Nixon, Mark; Lucas, Michael, Smart process modules and objects in process plants.
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  45. Schleiss,Duncan; Ramachandran,Ram; Nixon,Mark; Lucas,Michael, Smart process modules and objects in process plants.
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  46. Blevins, Terrence; Nixon, Mark; Lucas, Michael; Webb, Arthur; Beoughter, Ken, Smart process objects used in a process plant modeling system.
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  47. Law, Gary K.; Ott, Michael G.; Burr, Kent A.; Sherriff, Godfrey R., State machine function block with a user modifiable state transition configuration database.
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  48. Law, Gary K.; Ott, Michael G.; Burr, Kent A.; Sherriff, Godfrey R., State machine function block with a user modifiable state transition configuration database.
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  49. Law, Gary K.; Sherriff, Godfrey R., State machine function block with user-definable actions on a transition between states.
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  50. Ogami, Kenneth; Best, Andrew; Zhaksilikov, Marat, System and method for controlling a target device.
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  51. Feldman, Michael, System and method for generating distributed information systems.
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  52. Devereux, Brian M., System and method for mapping component bases using a chemical process simulator.
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  53. Devereux, Brian M., System and method for simulating operation of substructures of a chemical processing plant.
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  54. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.
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  55. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.
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  56. Ogami, Kenneth Y.; Anderson, Doug; Pleis, Matthew; Hood, Rick, Techniques for generating microcontroller configuration information.
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  57. Venkataraman, Garthik; Kutz, Harold; Mar, Monte, Temperature sensor with digital bandgap.
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  58. Snyder, Warren; Sullam, Bert; Mohammed, Haneef, Universal digital block interconnection and channel routing.
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  59. Blevins, Terrence L.; Wojsznis, Wilhelm K.; Nixon, Mark J., Updating and utilizing dynamic process simulation in an operating process environment.
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  60. Blevins, Terrence L.; Wojsznis, Wilhelm K.; Nixon, Mark J., Updating and utilizing dynamic process simulation in an operating process environment.
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  61. Blevins, Terrence L.; Wojsznis, Wilhelm K.; Nixon, Mark J., Updating and utilizing dynamic process simulation in an operating process environment.
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  62. Havekost, Robert B.; Nixon, Mark J., User configurable alarms and alarm trending for process control system.
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  63. Bartz, Manfred; Zhaksilikov, Marat; Anderson, Doug, User interface for efficiently browsing an electronic document using data-driven tabs.
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  64. Sivadasan, Mohandas Palatholmana; Rohilla, Gajendar, Voltage controlled oscillator delay cell and method.
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