초록 ▼

A computer system is provided which includes at least two microprocessors. The first microprocessor is configured to translate instructions from an original computer program coded in a first instruction set to a translated computer program coded in a second instruction set. The second microprocessor

A computer system is provided which includes at least two microprocessors. The first microprocessor is configured to translate instructions from an original computer program coded in a first instruction set to a translated computer program coded in a second instruction set. The second microprocessor is configured to execute the translated program. In one particular embodiment, the original program is coded in the x86 instruction set and the translated program is coded in the ADSP 2171 instruction set. Instead of manually performing the translation, the translation is automatically performed by the computer system upon invocation of the original computer program. Those computer programs which may be more efficiently executed by the second microprocessor may be translated into the instruction set executed by the second microprocessor. In one embodiment, the translation of the computer program is performed in page-sized portions. The first microprocessor translates a first page of the original computer program. While the first microprocessor translates a second page of the original computer program, the second microprocessor begins execution of the first page of translated instructions.

대표청구항 ▼

[ What is claimed is:] [1.] A computer system, comprising:a first microprocessor configured to translate a first computer program coded in a first instruction set into a second computer program coded in a second instruction set different from said first instruction set, said first computer program b

[ What is claimed is:] [1.] A computer system, comprising:a first microprocessor configured to translate a first computer program coded in a first instruction set into a second computer program coded in a second instruction set different from said first instruction set, said first computer program being executable in said first microprocessor even without translation;a buffer coupled to said first microprocessor, wherein said buffer includes a first portion and a second portion, said first and second portions being configured to store translated instructions which comprise said second computer program; anda second microprocessor coupled to said buffer and configured to execute translated instructions from either said first portion or said second portion of said buffer;wherein said first portion is filled with translated instructions at the same time said second processor executes translated instructions stored in said second portion; andwherein said first microprocessor, said buffer, and said second microprocessor are integrated upon a common substrate.