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Method of manufacturing a semiconductor chip carrier 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-003/30
  • H01R-009/00
출원번호 US-0465146 (1995-06-05)
발명자 / 주소
  • Crane
  • Jr. Stanford W.
  • Portuondo Maria M.
출원인 / 주소
  • The Panda Project
대리인 / 주소
    Morgan, Lewis & Bockius LLP
인용정보 피인용 횟수 : 15  인용 특허 : 43

초록

A semiconductor die carrier includes a plurality of electrically insulative side walls; a plurality of electrically conductive leads extending from at least one of the side walls, each of the leads being individually manufactured without use of a lead frame; a semiconductor die positioned such that

대표청구항

[ What is claimed is:] [37.] A method of manufacturing a semiconductor die carrier, comprising the steps of:forming a plurality of substantially L-shaped conductive leads;forming a carrier substrate for holding a semiconductor die, the substrate having a plurality of insulative side walls defining a

이 특허에 인용된 특허 (43)

  1. Frei John K. (Mesa AZ) Brice-Heames Kenneth (Mesa AZ), Apparatus for adapting semiconductor die pads and method therefor.
  2. Crane ; Jr. Stanford W. (Boca Raton FL) Portuondo Maria M. (Delray Beach FL), Apparatus having inner layers supporting surface-mount components.
  3. Sucheski Matthew M. (Harrisburg PA) Barkus Lee A. (Millersburg PA), Coaxial contact element.
  4. Kondo Mitsuhiro (Oogaki JPX) Watanabe Osamu (Oogaki JPX), Encapsulated semiconductor device with bridge sealed lead frame.
  5. Sugimoto Masahiro (Yokosuka JPX) Wakasugi Yasumasa (Kawasaki JPX) Harada Shigeki (Kawasaki JPX), Heatsink package for flip-chip IC.
  6. Shaheen Joseph M. (La Habra CA) Yamaguchi James S. (Lake Forest CA), Hermetic organic/inorganic interconnection substrate for hybrid circuit manufacture.
  7. Frankeny, Jerome A.; Frankeny, Richard F.; Haj-Ali-Ahmadi, Javad; Hermann, Karl; Imken, Ronald L., High density interconnect strip.
  8. Desai Kishor V. (Vestal NY) Macek Thomas G. (Endicott NY) Patel Maganlal S. (Endicott NY) Thomas Edwin L. (Apalachin NY), High density, separable connector and contact for use therein.
  9. Boucard Michel R. J. (Tournefeuille FRX) Francois Thirion C. (Auterive FRX), Housing for an electronic circuit.
  10. Krumme John F. (Woodside CA) Hodgson Darel E. (Palo Alto CA), Integrated circuit package and seal therefor.
  11. Tukamoto Takashi (Suwa JPX) Abe Sachiyuki (Suwa JPX) Yabushita Tetsuo (Suwa JPX) Hayashi Yoshimitsu (Suwa JPX), Integrated circuit package for flexible computer system alternative architectures.
  12. Kuroda Masao (Aichi JPX), Integrated-circuit package.
  13. Nelson Gregory H. (Gilbert AZ) Lebow Sanford (Westlake CA) Nogavich Eugene (Gilbert AZ), Interconnect device and method of manufacture thereof.
  14. Masayuki Watanabe (Yokohama JPX) Toshio Sugano (Kokubunji JPX) Seiichiro Tsukui (Komoro JPX) Takashi Ono (Akita JPX) Yoshiaki Wakashima (Kawasaki JPX), Lead connections means for stacked tab packaged IC chips.
  15. Shaffer Howard R. (Millersburg PA), Limited insertion force contact terminals and connectors.
  16. Krum Alvin L. (Huntington Beach CA) Conklin Charles W. (Huntington Beach CA), Low resistance electrical interconnection for synchronous rectifiers.
  17. Gregoire George D. (9927 Aviary Dr. San Diego CA 92131), Method and apparatus for making printed circuit boards.
  18. Kobayashi Yasushi (Kamikodanaka JPX) Kogure Seiji (Nakahara JPX), Method for encapsulting IC chip.
  19. Koepke Richard A. (New Bedford MA) Koepke George O. (Rochester NY), Method for fabricating a fold-up frame.
  20. Gregoire George D. (9927 Aviary Dr. San Diego CA 92131), Method for making printed circuit boards.
  21. Hingorany Prem R. (Broomfield CO), Method of manufacture power hybrid microcircuit.
  22. Crane ; Jr. Stanford W. (Boca Raton FL) Portuondo Maria M. (Delray Beach FL), Method of manufacturing a semiconductor chip carrier affording a high-density external interface.
  23. Crane ; Jr. Stanford W. (Boca Raton FL) Portuondo Maria M. (Delray Beach FL), Method of manufacturing an apparatus having inner layers supporting surface-mount components.
  24. Gregoire George D. (San Diego CA), Method of mounting a surface-mountable IC to a converter board.
  25. Watanabe Tamio (Shizuoka JPX), Method of producing terminal for base board.
  26. Reylek Robert S. (St. Paul MN) Thompson Kenneth C. (St. Paul MN), Miniature multiple conductor electrical connector.
  27. Taniuchi Kenjiro (Kawasaki JPX) Miyazawa Hideo (Kawasaki JPX) Ishikawa Kouji (Kawasaki JPX) Watanabe Kouji (Kawasaki JPX), Mounting device for mounting an electronic device on a substrate by the surface mounting technology.
  28. Martens John D. (Plano TX) Ammon J. Preston (Dallas TX), Multi row high density connector.
  29. Feng Bai-Cwo (Tarrytown NY) Feng George C. (Fishkill NY) McMaster Richard H. (Wappingers Falls NY), Multi-layer package incorporating a recessed cavity for a semiconductor chip.
  30. Hirano Naohiko (Yokohama JPX), Multilayer package.
  31. Tillotson John (Southfield MI), Multiple contact header assembly.
  32. Griswold Bradley L. (San Jose CA) Ho Chung W. (Monte Sereno CA) Robinette ; Jr. William C. (Los Altos CA), Packaging and interconnect system for integrated circuits.
  33. Buck Jonathan E. (Harrisburg PA) Rose William H. (Harrisburg PA), Paired contact electrical connector system.
  34. Shirling David J. (Waterbury CT), Pin grid array having seperate posts and socket contacts.
  35. Ammon J. Preston (Dallas TX) Weaver Harry R. (Dallas TX) Evans Evan J. (Plano TX), Printed circuit board finger connector.
  36. Utunomiya Jiro (Tokyo JPX) Iida Saburo (Tokyo JPX) Sibuya Hitosi (Tokyo JPX) Kusaba Kazunori (Tokyo JPX) Narumi Isao (Tokyo JPX), Process of assembling terminal structure.
  37. Brown Candice H. (San Jose CA), Process of making a semiconductor device having parallel leads directly connected perpendicular to integrated circuit la.
  38. Arima Hideo (Yokohama JPX) Takeda Kenji (Kamakura JPX) Yamamura Hideho (Yokohama JPX) Kobayashi Fumiyuki (Sagamihara JPX), Semiconductor chip carrier, module having same chip carrier mounted therein, and electronic device incorporating same mo.
  39. Kohara Masanobu (Itami JPX) Kondo Takashi (Itami JPX) Yama Yomiyuki (Itami JPX), Semiconductor device and package.
  40. Jurista Thomas M. (Vestal NY) Mantilla Osvaldo A. (Endicott NY), Sequential Connecting device.
  41. Seidler Jack (Flushing NY), Solder-bearing lead.
  42. Dutta Vivek B. (Cupertino CA) Demmin Jeffrey C. (Mt. View CA) DiOrio Mark L. (Cupertino CA) Ewanich Jon T. (Cupertino CA), Stadium-stepped package for an integrated circuit with air dielectric.
  43. Juskey Frank J. (Coral Springs FL) Suppelsa Anthony B. (Coral Springs FL), Thermally conductive integrated circuit package with radio frequency shielding.

이 특허를 인용한 특허 (15)

  1. Crane, Jr., Stanford W.; Larcomb, Daniel; Krishnapura, Lakshminarasimha, Apparatus for and method of manufacturing a semiconductor die carrier.
  2. Fjelstad,Joseph C.; Segaram,Para K.; Haba,Belgacem, Direct-connect integrated circuit signaling system for bypassing intra-substrate printed circuit signal paths.
  3. Fjelstad, Joseph C.; Segaram, Para K.; Haba, Belgacem, Direct-connect signaling system.
  4. Glenn Thomas P., Electrostatic discharge protection package and method.
  5. Fjelstad, Joseph C.; Grundy, Kevin P.; Yasumura, Gary, IC package structures having separate circuit interconnection structures and assemblies constructed thereof.
  6. Crane ; Jr. Stanford W. ; Krishnapura Lakshminarasimha ; Dutta Arindum, Integrated connector and semiconductor die package.
  7. Wang, Ching-Shun, Method for manufacturing and packaging integrated circuit.
  8. Gall Peter J., Method of fabricating integrated circuit package with opening allowing access to die.
  9. Egitto, Frank D.; Farquhar, Donald S.; Markovich, Voya R.; Poliks, Mark D.; Powell, Douglas O., Multi-layered interconnect structure using liquid crystalline polymer dielectric.
  10. Egitto, Frank D.; Farquhar, Donald S.; Markovich, Voya R.; Poliks, Mark D.; Powell, Douglas O., Multi-layered interconnect structure using liquid crystalline polymer dielectric.
  11. Egitto, Frank D.; Farquhar, Donald S.; Markovich, Voya R.; Poliks, Mark D.; Powell, Douglas O., Multi-layered interconnect structure using liquid crystalline polymer dielectric.
  12. Egitto,Frank D.; Farquhar,Donald S.; Markovich,Voya R.; Poliks,Mark D.; Powell,Douglas O., Multi-layered interconnect structure using liquid crystalline polymer dielectric.
  13. Fjelstad, Joseph C.; Haba, Belgacem, Multi-path via interconnection structures and methods for manufacturing the same.
  14. Jae Hoon Kim KR, Semiconductor chip package with multilevel leads.
  15. Fjelstad,Joseph C.; Segaram,Para; Obenhuber,Thomas; Yasumura,Gary, System for making high-speed connections to board-mounted modules.
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