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Semiconductor device, production method therefor, method for testing semiconductor elements, test substrate for the meth 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G01R-031/02
출원번호 US-0753882 (1996-12-02)
우선권정보 JP-0030341 (1994-02-28)
발명자 / 주소
  • Hamaguchi Tsuneo,JPX
  • Kagata Kenji,JPX
  • Izuta Goro,JPX
  • Ishizaki Mitsunori,JPX
  • Hayashi Osamu,JPX
  • Hoshinouchi Susumu,JPX
출원인 / 주소
  • Mitsubishi Denki Kabushiki Kaisha, JPX
대리인 / 주소
    Sughrue, Mion, Zinn, Macpeak & Seas, PLLC
인용정보 피인용 횟수 : 30  인용 특허 : 5

초록

A high-speed, high-density, small-sized, low-cost semiconductor device wherein the feeder substrate 2 for supplying power to the semiconductor elements 3 as a bare chip has the containers 2a for containing the semiconductor elements 3, the semiconductor elements 3 are bonded to the wiring layer 1b o

대표청구항

[ What is claimed is:] [1.] A method for testing a semiconductor element having electrical connection electrodes which comprises the steps of:forming protruding electrodes on a test substrate having test wires to electrically connect the protruding electrodes with the test wires;bonding the electric

이 특허에 인용된 특허 (5)

  1. Beaumont Guy D. (Granby CAX) Labbe Denis (Granby CAX) Warren Alain (Granby CAX), Apparatus and method for creating detachable solder connections.
  2. Koepf Gerhard A. (Boulder CO), Interconnect package having means for waveguide transmission of RF signals.
  3. Gupta Debabrata (Scottsdale AZ) Drye James E. (Mesa AZ), Multiple integrated circuit module which simplifies handling and testing.
  4. Bureau Jean-Marc (Palaiseau FRX) Bernard Francois (Les Ulis FRX) Broussoux Dominique (Marcoussis FRX) Vergnolle Claude (Limours FRX), Process for manufacturing a multilayer integrated circuit interconnection.
  5. Zappella Pierino I. (Garden Grove CA) Fewer William R. (Diamond Bar CA), Transferable solder bumps for interconnect and assembly of MCM substrates.

이 특허를 인용한 특허 (30)

  1. Rabarot Marc,FRX ; Fulbert Laurent,FRX, Assembly procedure for two structures and apparatus produced by the procedure applications to microlasers.
  2. Nathan, Richard J., Embedded carrier for an integrated circuit chip.
  3. Hugo, Stephen M.; Lewis, Theron L., Laminate bond strength detection.
  4. Gunter Igel DE; Ulrich Sieben DE; Jurgen Giehl DE; Bernhard Wolf DE, Measuring device.
  5. Ohtaki, Mikio, Method for manufacturing and batch testing semiconductor devices.
  6. Ohtaki,Mikio, Method for manufacturing and testing semiconductor devices on a resin-coated wafer.
  7. Giri, Ajay Prabhakar; Sullivan, Joseph Michael; Tessler, Christopher Lee, Method of forming a multichip module having chips on two sides.
  8. Standing, Martin; Pawley, Marcus; Roberts, Andrew; Clarke, Robert, Method of inserting an electronic component into a slot in a circuit board.
  9. Ohtaki, Mikio, Method of testing circuit elements on a semiconductor wafer.
  10. Loo, Howe Yin; Chee, Choong Kooi, Microelectronic device attachment on a reverse microelectronic package.
  11. Loo, Howe Yin; Chee, Choong Kooi, Microelectronic device attachment on a reverse microelectronic package.
  12. Higashitani,Hiroshi; Yasuho,Takeo; Hayama,Masaaki, Module part.
  13. Higashitani,Hiroshi; Yasuho,Takeo; Hayama,Masaki, Module part.
  14. Hofstee, Harm Peter; Montoye, Robert Kevin; Sprogis, Edmund Juris, Multi-chip integrated circuit module.
  15. Yinon Degani ; Thomas Dixon Dudderar ; King Lien Tai, Packaging silicon on silicon multichip modules.
  16. Mikio Ohtaki JP, Semiconductor device test apparatus.
  17. Korony, Gheorghe, Shaped integrated passives.
  18. Sweterlitsch, Jennifer R., Stacked package for integrated circuits.
  19. Bowers, Jeffrey A.; Hyde, Roderick A.; Ishikawa, Muriel Y.; Jung, Edward K. Y.; Kare, Jordin T.; Leuthardt, Eric C.; Myhrvold, Nathan P.; Nugent, Jr., Thomas J.; Tegreene, Clarence T.; Whitmer, Charles; Wood, Jr., Lowell L., Storage container including multi-layer insulation composite material having bandgap material.
  20. Standing, Martin; Roberts, Andrew, System and method of providing a semiconductor carrier and redistribution structure.
  21. Standing, Martin; Roberts, Andrew, System and method of providing a semiconductor carrier and redistribution structure.
  22. Eckhoff, Philip A.; Gates, William; Hyde, Roderick A.; Jung, Edward K. Y.; Myhrvold, Nathan P.; Peterson, Nels R.; Tegreene, Clarence T.; Whitmer, Charles; Wood, Jr., Lowell L., Temperature-controlled storage systems.
  23. Hyde, Roderick A.; Jung, Edward K. Y.; Myhrvold, Nathan P.; Tegreene, Clarence T.; Gates, William; Whitmer, Charles; Wood, Jr., Lowell L., Temperature-stabilized medicinal storage systems.
  24. Deane, Geoffrey F.; Fowler, Lawrence Morgan; Gates, William; Guo, Zihong; Hyde, Roderick A.; Jung, Edward K. Y.; Kare, Jordin T.; Myhrvold, Nathan P.; Pegram, Nathan; Peterson, Nels R.; Tegreene, Clarence T.; Whitmer, Charles; Wood, Jr., Lowell L., Temperature-stabilized storage systems.
  25. Hyde, Roderick A.; Jung, Edward K. Y.; Myhrvold, Nathan P.; Tegreene, Clarence T.; Gates, III, William H.; Whitmer, Charles; Wood, Jr., Lowell L., Temperature-stabilized storage systems.
  26. Chou, Fong-Li; Deane, Geoffrey F.; Gates, William; Guo, Zihong; Hyde, Roderick A.; Jung, Edward K. Y.; Myhrvold, Nathan P.; Peterson, Nels R.; Tegreene, Clarence T.; Whitmer, Charles; Wood, Jr., Lowell L., Temperature-stabilized storage systems with flexible connectors.
  27. Bloedow, Jonathan; Calderon, Ryan; Friend, Michael; Gasperino, David; Gates, William; Hyde, Roderick A.; Jung, Edward K. Y.; Liu, Shieng; Myhrvold, Nathan P.; Pegram, Nathan John; Piech, David Keith; Stone, Shannon Weise; Tegreene, Clarence T.; Whitmer, Charles; Wood, Jr., Lowell L.; Yildirim, Ozgur Emek, Temperature-stabilized storage systems with integral regulated cooling.
  28. Bloedow, Jonathan; Calderon, Ryan; Gasperino, David; Gates, William; Hyde, Roderick A.; Jung, Edward K. Y.; Liu, Shieng; Myhrvold, Nathan P.; Pegram, Nathan John; Tegreene, Clarence T.; Whitmer, Charles; Wood, Jr., Lowell L.; Yildirim, Ozgur Emek, Temperature-stabilized storage systems with regulated cooling.
  29. Yamaguchi, Miho; Hotta, Yuji, Test method of semiconductor device.
  30. Alcoe,David J.; Brodsky,William L.; Calmidi,Varaprasad V.; Sathe,Sanjeev B.; Stutzman,Randall J., Thermally enhanced lid for multichip modules.
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