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Multi-tasking sequencer for a TDMA burst mode controller

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H04Q-007/30
  • H04Q-007/32
출원번호 US-0621266 (1996-03-21)
발명자 / 주소
  • Weigand David L.
  • Malek Charles J.
출원인 / 주소
  • National Semiconductor Corporation
대리인 / 주소
    Skjerven, Morrill, MacPherson, Franklin & FranklinOgonowsky
인용정보 피인용 횟수 : 58  인용 특허 : 1

초록

A multi-tasking, dynamically controlled micro-sequencer for use in a TDMA communication system is described. Rather than the output of the sequencer being solely a linear sequence of instructions in a microcode RAM, the output of the sequencer is augmented by an output of finite state machines (FSMs

대표청구항

[ What is claimed is:] [1.] A system for use in TDMA communication network, said network transmitting and receiving bursts of data within time slots, said data in a slot being arranged in accordance with one or more protocols, said system including a sequencer comprising:a microcode memory;a logic d

이 특허에 인용된 특허 (1)

  1. Levy Jonathan (Kfar-Saba ILX), Generating real-time events in a TDMA digital wireless communications system.

이 특허를 인용한 특허 (58)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  16. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  17. Master,Paul L.; Scheuermann,W. James, Configurable finite state machine for operation of microinstruction providing execution enable control value.
  18. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  19. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  20. Beard, Timothy Giles; Cooper, David Edward, Extended dynamic resource allocation in packet data transfer.
  21. Beard,Timothy Giles; Cooper,David Edward, Extended dynamic resource allocation in packet data transfer.
  22. Beard,Timothy Giles; Cooper,David Edward, Extended dynamic resource allocation in packet data transfer.
  23. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  24. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  25. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  26. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  27. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  28. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  29. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  30. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  31. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  32. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  33. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  34. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  35. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  36. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  37. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  38. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  39. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  40. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  41. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  42. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  43. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  44. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  45. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  46. Weigand, David, Microsequencer microcode bank switched architecture.
  47. Weigand, David, Microwire dynamic sequencer pipeline stall.
  48. Narasimhan, Ravi, Multicarrier transmit diversity.
  49. Narasimhan, Ravi, Multicarrier transmit diversity.
  50. Narasimhan, Ravi, Multicarrier transmit diversity.
  51. Hill Gregory A., Multiport data buffer having multi level caching wherein each data port has a FIFO buffer coupled thereto.
  52. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  53. Master,Paul L.; Watson,John, Storage and delivery of device features.
  54. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  55. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  56. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  57. Loukianov Dmitrii, Versatile time division multiple access slot assignment unit.
  58. Loukianov, Dmitril, Versatile time division multiple access slot assignment unit.
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