초록 ▼

A memory block structure for use within a viterbi decoder includes multiple dual port RAMs configured as multiport RAMs. The memory block structure is configured to allow a one-word write operation and an N-word read operation during a single clock cycle in order to achieve one decoded output symbol

A memory block structure for use within a viterbi decoder includes multiple dual port RAMs configured as multiport RAMs. The memory block structure is configured to allow a one-word write operation and an N-word read operation during a single clock cycle in order to achieve one decoded output symbol per clock period using the viterbi algorithm. By using dual port RAMs, a more densely packed and less expensive memory block structure is achieved. An encoded stream of input symbols are input to the viterbi decoder and written to the memory block structure one word at a time. Once X+Y bits have been written to the memory block structure, the decoder will then read N words from the memory block structure, simultaneously, reading back through X+Y words and outputting Y bits N at a time at the end of the trace back through memory. This process is repeated once the next Y words have been written to the memory block 22, with X+Y words being traced back through and the appropriate Y bits being output, until the entire encoded stream of input symbols has been decoded.

대표청구항 ▼

[ We claim:] [1.] A viterbi decoder for decoding an input stream of encoded symbols and outputting appropriate decoded symbols comprising:a. means for receiving encoded data from an input source;b. control means coupled to the means for receiving for controlling operation of the viterbi decoder for

[ We claim:] [1.] A viterbi decoder for decoding an input stream of encoded symbols and outputting appropriate decoded symbols comprising:a. means for receiving encoded data from an input source;b. control means coupled to the means for receiving for controlling operation of the viterbi decoder for receiving a plurality of stored data on which to perform a trace back operation outputting one decoded symbol per clock cycle; andc. a dual port memory structure having a plurality of dual port RAMs, wherein the memory structure is coupled to the means for receiving and to the control means for storing one word of encoded data received from the input source and transmitting the plurality of stored data to the control means during a single clock cycle, further wherein the dual port RAMs are coupled to receive a same read enable signal.