초록 ▼

The Parallel DSP Chip has a general purpose, reduced instruction set for parallel digital signal processing. The following pertains to the preferred embodiment. Most instruction words are 32 bits long and execute at the rate of one per clock cycle. Each instruction word is executed by a single, pipe

The Parallel DSP Chip has a general purpose, reduced instruction set for parallel digital signal processing. The following pertains to the preferred embodiment. Most instruction words are 32 bits long and execute at the rate of one per clock cycle. Each instruction word is executed by a single, pipelined instruction unit that controls the operation of four, 16-bit vector processors in parallel with one group of bits, and the operation of a 24-bit scalar processor with another group of bits. Thus five instructions are typically executed for every instruction word as a result of the parallel architecture. A single, linear, 16 MB, memory address space is used, simplifying program development. The storage of 8- and 16-bit operands for use by the vector processors is supported to maximize memory utilization. The Parallel DSP Chip is specifically designed to support an enhanced C compiler and has two software stack pointers, one for the vector processors and one for the scalar processor, plus an interrupt stack pointer. The Parallel DSP Chip executes a single task in parallel. Using an enhanced C compiler, simple, familiar, scalar processing programming techniques can be used, and a simple, single-task operating system can be used for software development. The basic programming concept is to define one or more arrays of four-element structures using the enhanced C compiler. One element in such a structure is provided for each of the four vector processors. The structure to be processed at any one time is selected by an address computed by the scalar processor. The same operation is applied to all of the elements of the structure by the simultaneous operation of the vector processors. To access the next structure in an array of structures, the scalar processor advances the address by the number of bytes in the structure.

대표청구항 ▼

[ I claim:] [1.] A method for operating a digital data processor, comprising the steps of:accessing a first instruction from a memory that is coupled to a digital data processor, the digital data processor comprising a first processing element and a plurality of second processing elements, the first

[ I claim:] [1.] A method for operating a digital data processor, comprising the steps of:accessing a first instruction from a memory that is coupled to a digital data processor, the digital data processor comprising a first processing element and a plurality of second processing elements, the first instruction being comprised of a plurality of fields;applying the accessed first instruction to the digital data processor;controlling an operation of the first processing element of the digital data processor with m first fields of the accessed instruction, where m is a positive integer that is greater than or equal to one; andsimultaneously controlling an operation of each of the plurality of second processing elements of the digital data processor with n second fields of the accessed instruction, where n is greater than or equal to one, said n second fields providing identical control to the plurality of second processing elements;wherein each of the first processing element and the plurality of second processing elements is comprised of an addressable register bank for storing operands, wherein each of the first processing element and the plurality of second processing elements is comprised of logic means for performing an operation on operands read out from an associated one of the register banks, wherein the m first fields of the instruction control the first processing element by specifying a first register within the register bank, a second register within the register bank, and an operation to be performed by the logic means on operands read out from the specified first and second registers, and wherein the n second fields of the instruction control each of the plurality of second processing elements by specifying, for each of the plurality of second processing elements, a first register within the register bank, a second register within the register bank, and an operation to be performed by the logic means on operands read out from the specified first and second registers.