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Protected encapsulation of catalytic layer for electroless copper interconnect 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0587264 (1996-01-16)
발명자 / 주소
  • Schacham-Diamand Yosef
  • Dubin Valery M.
  • Ting Chiu H.
  • Zhao Bin
  • Vasudev Prahalad K.
  • Desilva Melvin
출원인 / 주소
  • Sematech, Inc.
인용정보 피인용 횟수 : 366  인용 특허 : 9

초록

A method for utilizing electroless copper deposition to form interconnects on a semiconductor. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum

대표청구항

[ We claim:] [1.] A method of forming a protected catalytic seed surface in order to deposit metal by electroless deposition to form an interconnect structure on a semiconductor wafer, comprising the steps of:depositing a barrier layer;depositing a catalytic seed layer on said barrier layer under va

이 특허에 인용된 특허 (9)

  1. Shacham Yosef Y. (Ithaca NY) Bielski Roman (Ithaca NY), Alkaline free electroless deposition.
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  6. Gilton Terry L. (Boise ID) Tuttle Mark E. (Boise ID) Cathey David A (Boise ID), Process for metallizing integrated circuits with electrolytically-deposited copper.
  7. Hirsch Tom J. (Austin) Lin Charles W. C. (San Antonio) Lee Chung J. (Austin) Muller Heinrich G. O. (Austin TX), Protective layer for preventing electroless deposition on a dielectric.
  8. Baum Thomas H. (San Jose CA) Houle Frances A. (Fremont CA) Jones Carol R. (San Jose CA) Kovac Caroline A. (Ridgefield CT), Selective deposition of copper.
  9. Hoshino Kazuhiro (Tokyo JPX), Semiconductor device using copper metallization.

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